Issued Patents 2025
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412851 | Semiconductor device and method of manufacture | Po-Hao Tsai, Ming-Chih Yew, Shin-Puu Jeng | 2025-09-09 |
| 12388028 | Package structure | Yi-Wen Wu, Shin-Puu Jeng, Shih-Ting Hung | 2025-08-12 |
| 12362341 | Semiconductor devices and methods of manufacturing | Chang-Yi Yang, Shin-Puu Jeng | 2025-07-15 |
| 12354989 | Package structure with conductive via structure | Meng-Liang Lin, Shin-Puu Jeng | 2025-07-08 |
| 12308313 | Semiconductor package with improved interposer structure | Yi-Wen Wu, Techi Wong, Po-Hao Tsai, Shih-Ting Hung, Shin-Puu Jeng | 2025-05-20 |
| 12308322 | Dual-sided routing in 3D semiconductor system-in-package structure and methods of forming the same | Po-Hao Tsai, Meng-Liang Lin, Yi-Wen Wu, Shin-Puu Jeng, Techi Wong | 2025-05-20 |
| 12300592 | Fan-out package with controllable standoff | Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Shin-Puu Jeng | 2025-05-13 |
| 12237262 | Semiconductor package with improved interposer structure | Yi-Wen Wu, Techi Wong, Po-Hao Tsai, Shih-Ting Hung, Shin-Puu Jeng | 2025-02-25 |
| 12224266 | Semiconductor packages including passive devices and methods of forming same | Shin-Puu Jeng, Shuo-Mao Chen | 2025-02-11 |
| 12205861 | Manufacturing method of semiconductor package including forming cavity in circuit substrate without exposing floor plate | Meng-Liang Lin, Te-Chi Wong, Shuo-Mao Chen, Shin-Puu Jeng | 2025-01-21 |
| 12198996 | Integrated fan-out package, package-on-package structure, and manufacturing method thereof | Shin-Puu Jeng, Hsien-Wen Liu, Shih-Ting Hung, Yi-Jou Lin, Tzu-Jui Fang | 2025-01-14 |
| 12199084 | Fan-out package with cavity substrate | Po-Hao Tsai, Techi Wong, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin | 2025-01-14 |
| 12191261 | Semiconductor device including electromagnetic interference (EMI) shielding and method of manufacture | Meng-Wei Chou, Shin-Puu Jeng | 2025-01-07 |