Issued Patents 2024
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12165920 | Semiconductor structure and method for forming the same | Hwei-Jay CHU, Chieh-Han Wu, Cheng-Hsiung Tsai | 2024-12-10 |
| 12125795 | Integrated chip with inter-wire cavities | Hsin-Chieh Yao, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai +2 more | 2024-10-22 |
| 12094823 | Interconnection structure and methods of forming the same | Wei-Hao Liao, Hsi-Wen Tien, Yu-Teng Dai, Chih Wei Lu, Hsin-Chieh Yao | 2024-09-17 |
| 12074059 | Semiconductor arrangement and method of making | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu | 2024-08-27 |
| 12046551 | Interconnect structure having a barrier layer along the sidewall of self-aligned via structures | Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu | 2024-07-23 |
| 11972975 | Semiconductor device structure having air gap and method for forming the same | Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih Wei Lu +1 more | 2024-04-30 |
| 11955376 | Etch damage and ESL free dual damascene metal interconnect | Sunil Kumar Singh, Tien-I Bao | 2024-04-09 |
| 11942364 | Selective deposition of a protective layer to reduce interconnect structure critical dimensions | Hsi-Wen Tien, Chih Wei Lu, Hsin-Chieh Yao, Yu-Teng Dai, Wei-Hao Liao | 2024-03-26 |
| 11929258 | Via connection to a partially filled trench | Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Tien-I Bao +1 more | 2024-03-12 |
| 11923293 | Barrier structure on interconnect wire to increase processing window for overlying via | Hsin-Chieh Yao, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai | 2024-03-05 |
| 11915943 | Methods of etching metals in semiconductor devices | Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai | 2024-02-27 |
| 11894238 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen +4 more | 2024-02-06 |