KC

Kangguo Cheng

IBM: 64 patents #4 of 6,852Top 1%
TE Tessera: 9 patents #1 of 63Top 2%
AS Adeia Semiconductor Solutions: 1 patents #1 of 1Top 100%
📍 Schenectady, NY: #1 of 103 inventorsTop 1%
🗺 New York: #2 of 11,993 inventorsTop 1%
Overall (2023): #147 of 537,848Top 1%
74
Patents 2023

Issued Patents 2023

Showing 1–25 of 74 patents

Patent #TitleCo-InventorsDate
11848357 Strained superlattice Juntao Li, Shogo Mochizuki 2023-12-19
11848384 Semiconductor device with airgap spacer formation from backside of wafer Ruilong Xie, Julien Frougier, Chanro Park 2023-12-19
11843031 Short gate on active and longer gate on STI for nanosheets Chen Zhang, Wenyu Xu, Ruilong Xie 2023-12-12
11837604 Forming stacked nanosheet semiconductor devices with optimal crystalline orientations around devices Shogo Mochizuki, Juntao Li 2023-12-05
11830946 Bottom source/drain for fin field effect transistors Heng Wu, Shogo Mochizuki, Gen Tsutsui 2023-11-28
11825757 Memory device having a ring heater 2023-11-21
11823956 Two-dimensional vertical fins 2023-11-21
11812675 Filament confinement in resistive random access memory Juntao Li, Dexin Kong, Zheng Xu 2023-11-07
11805704 Via interconnects for a magnetoresistive random-access memory device Julien Frougier, Dimitri Houssameddine, Ruilong Xie 2023-10-31
11798851 Work function metal patterning for nanosheet CFETs Ruilong Xie, Chen Zhang, Juntao Li 2023-10-24
11798852 Hybrid-channel nano-sheet FETs Zhenxing Bi, Peng Xu, Wenyu Xu 2023-10-24
11791396 Field effect transistor with multiple gate dielectrics and dual work-functions with precisely controlled gate lengths Ruilong Xie, Julien Frougier, Chanro Park 2023-10-17
11791199 Nanosheet IC device with single diffusion break Ruilong Xie, Juntao Li, Carl Radens 2023-10-17
11791342 Varactor integrated with complementary metal-oxide semiconductor devices Julien Frougier, Ruilong Xie, Juntao Li 2023-10-17
11784125 Wrap around cross-couple contact structure with enhanced gate contact size Ruilong Xie, Chanro Park, Julien Frougier 2023-10-10
11779918 3D nanochannel interleaved devices Lawrence A. Clevenger, Donald F. Canaperi, Shawn P. Fetterolf 2023-10-10
11784095 Fabrication of a vertical fin field effect transistor with reduced dimensional variations 2023-10-10
11776956 III-V fins by aspect ratio trapping and self-aligned etch to remove rough epitaxy surface Jeehwan Kim 2023-10-03
11777275 Augmented semiconductor lasers with spontaneous emissions blockage Julien Frougier, Ruilong Xie, Chanro Park 2023-10-03
11764259 Vertical field-effect transistor with dielectric fin extension Chen Zhang, Tenko Yamashita, Xin Miao, Wenyu Xu 2023-09-19
11764265 Nanosheet transistor with inner spacers Ruilong Xie, Julien Frougier, Juntao Li 2023-09-19
11756957 Reducing gate resistance in stacked vertical transport field effect transistors Heng Wu, Chen Zhang, Tenko Yamashita, Joshua M. Rubin 2023-09-12
11738995 Manipulation of a molecule using dipole moments Lawrence A. Clevenger, Shawn P. Fetterolf, Donald F. Canaperi 2023-08-29
11742836 Random number generator using cross-coupled ring oscillators Carl Radens 2023-08-29
11735658 Tunnel field-effect transistor with reduced subthreshold swing Xin Miao, Chen Zhang, Wenyu Xu 2023-08-22