Issued Patents 2023
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11848384 | Semiconductor device with airgap spacer formation from backside of wafer | Ruilong Xie, Kangguo Cheng, Chanro Park | 2023-12-19 |
| 11805704 | Via interconnects for a magnetoresistive random-access memory device | Dimitri Houssameddine, Ruilong Xie, Kangguo Cheng | 2023-10-31 |
| 11804436 | Self-aligned buried power rail cap for semiconductor devices | Ruilong Xie, Huimei Zhou, Kisik Choi | 2023-10-31 |
| 11791396 | Field effect transistor with multiple gate dielectrics and dual work-functions with precisely controlled gate lengths | Kangguo Cheng, Ruilong Xie, Chanro Park | 2023-10-17 |
| 11791342 | Varactor integrated with complementary metal-oxide semiconductor devices | Kangguo Cheng, Ruilong Xie, Juntao Li | 2023-10-17 |
| 11784125 | Wrap around cross-couple contact structure with enhanced gate contact size | Ruilong Xie, Kangguo Cheng, Chanro Park | 2023-10-10 |
| 11777275 | Augmented semiconductor lasers with spontaneous emissions blockage | Kangguo Cheng, Ruilong Xie, Chanro Park | 2023-10-03 |
| 11764265 | Nanosheet transistor with inner spacers | Kangguo Cheng, Ruilong Xie, Juntao Li | 2023-09-19 |
| 11757036 | Moon-shaped bottom spacer for vertical transport field effect transistor (VTFET) devices | Ruilong Xie, Chen Zhang, Alexander Reznicek, Shogo Mochizuki | 2023-09-12 |
| 11742350 | Metal gate N/P boundary control by active gate cut and recess | Andrew Gaul, Chanro Park, Ruilong Xie, Andrew M. Greene, Christopher J. Waskiewicz | 2023-08-29 |
| 11735590 | Fin stack including tensile-strained and compressively strained fin portions | Kangguo Cheng, Ruilong Xie, Chanro Park | 2023-08-22 |
| 11729996 | High retention eMRAM using VCMA-assisted writing | Heng Wu, Ruilong Xie, Bruce B. Doris | 2023-08-15 |
| 11710768 | Hybrid diffusion break with EUV gate patterning | Eric R. Miller, Indira Seshadri, Andrew M. Greene, Veeraraghavan S. Basker | 2023-07-25 |
| 11688741 | Gate-all-around devices with isolated and non-isolated epitaxy regions for strain engineering | Andrew M. Greene, Jingyun Zhang, Sung-Dae Suk, Veeraraghavan S. Basker, Ruilong Xie | 2023-06-27 |
| 11688626 | Nanosheet transistor with self-aligned dielectric pillar | Ruilong Xie, Kangguo Cheng | 2023-06-27 |
| 11682715 | Forming nanosheet transistor using sacrificial spacer and inner spacers | Kangguo Cheng, Nicolas Loubet | 2023-06-20 |
| 11646306 | Co-integration of gate-all-around FET, FINFET and passive devices on bulk substrate | Veeraraghavan S. Basker, Andrew Gaul, Ruilong Xie | 2023-05-09 |
| 11621269 | Multi-level ferroelectric memory cell | Ruilong Xie | 2023-04-04 |
| 11605409 | MTJ-based analog memory device | Dimitri Houssameddine, Kangguo Cheng, Ruilong Xie | 2023-03-14 |
| 11605672 | Steep-switch field effect transistor with integrated bi-stable resistive system | Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng | 2023-03-14 |
| 11569361 | Nanosheet transistors with wrap around contact | Ruilong Xie, Kangguo Cheng, Chanro Park | 2023-01-31 |