Issued Patents 2021
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11171039 | Composite semiconductor substrate, semiconductor device and method for manufacturing the same | Min-Ying Tsai, Cheng-Ta Wu, Yeur-Luen Tu | 2021-11-09 |
| 11171015 | Multi-layered polysilicon and oxygen-doped polysilicon design for RF SOI trap-rich poly layer | Cheng-Ta Wu, Chen-Hao Chiang, Alexander Kalnitsky, Yeur-Luen Tu, Eugene Chen | 2021-11-09 |
| 11158534 | SOI substrate | Cheng-Ta Wu, Ming-Che Yang, Wei-Kung Tsai, Yong-En Syu, Yeur-Luen Tu +1 more | 2021-10-26 |
| 11069733 | Image sensor having improved full well capacity and related method of formation | Shyh-Fann Ting, Yen-Ting Chiang, Yeur-Luen Tu, Min-Ying Tsai | 2021-07-20 |
| 11063117 | Semiconductor device structure having carrier-trapping layers with different grain sizes | Yong-En Syu, Kuo-Hwa Tzeng, Ke-Dian Wu, Cheng-Ta Wu, Yeur-Luen Tu +2 more | 2021-07-13 |
| 11049797 | Method for manufacturing a semiconductor structure comprising a semiconductor device layer formed on a tem, porary substrate having a graded SiGe etch stop layer therebetween | Shih Pei Chou, Yeur-Luen Tu, Alexander Kalnitsky, Tung-I Lin, Wei-Li Chen | 2021-06-29 |
| 10971534 | Image sensor having improved full well capacity and related method of formation | Shyh-Fann Ting, Yen-Ting Chiang, Yeur-Luen Tu, Min-Ying Tsai | 2021-04-06 |
| 10971406 | Method of forming source/drain regions of transistors | Ching-Wei Tsai, Yeur-Luen Tu, Tung-I Lin, Wei-Li Chen | 2021-04-06 |
| 10957540 | Semiconductor epitaxy bordering isolation structure | Wen-Chin Chen, Cheng-Yi Wu, Ren-Hua Guo, Hsiang-Wei Liu, Chin-Szu Lee | 2021-03-23 |
| 10923503 | Semiconductor-on-insulator (SOI) substrate comprising a trap-rich layer with small grain sizes | Cheng-Ta Wu, Yeur-Luen Tu, Min-Ying Tsai, Alex Usenko | 2021-02-16 |
| 10889097 | Wafer debonding system and method | Chang-Chen Tsao, Kuo-Liang Lu, Ru-Liang Lee, Sheng-Hsiang Chuang, Yeur-Luen Tu +1 more | 2021-01-12 |