Issued Patents 2021
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11171039 | Composite semiconductor substrate, semiconductor device and method for manufacturing the same | Min-Ying Tsai, Yu-Hung Cheng, Yeur-Luen Tu | 2021-11-09 |
| 11171015 | Multi-layered polysilicon and oxygen-doped polysilicon design for RF SOI trap-rich poly layer | Yu-Hung Cheng, Chen-Hao Chiang, Alexander Kalnitsky, Yeur-Luen Tu, Eugene Chen | 2021-11-09 |
| 11164945 | SOI substrate, semiconductor device and method for manufacturing the same | Kuo-Hwa Tzeng, Chih-Hao Wang, Yeur-Luen Tu, Chung-Yi Yu | 2021-11-02 |
| 11158534 | SOI substrate | Yu-Hung Cheng, Ming-Che Yang, Wei-Kung Tsai, Yong-En Syu, Yeur-Luen Tu +1 more | 2021-10-26 |
| 11094583 | Method of forming a device having a doping layer and device formed | Chii-Ming Wu | 2021-08-17 |
| 11063117 | Semiconductor device structure having carrier-trapping layers with different grain sizes | Yu-Hung Cheng, Yong-En Syu, Kuo-Hwa Tzeng, Ke-Dian Wu, Yeur-Luen Tu +2 more | 2021-07-13 |
| 11024716 | Semiconductor structure and method for forming the same | Yi-Hsien Lee, Wei-Ming You, Ting-Chun Wang | 2021-06-01 |
| 11011641 | Flat STI surface for gate oxide uniformity in Fin FET devices | Cheng-Wei Chen, Shiu-Ko JangJian, Ting-Chun Wang | 2021-05-18 |
| 10950490 | Semiconductor device having isolation structures with different thicknesses | Chii-Ming Wu, Sen-Hong Syue, Cheng-Po Chau | 2021-03-16 |
| 10923503 | Semiconductor-on-insulator (SOI) substrate comprising a trap-rich layer with small grain sizes | Yu-Hung Cheng, Yeur-Luen Tu, Min-Ying Tsai, Alex Usenko | 2021-02-16 |