Issued Patents 2021
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11164948 | Field-effect transistor and method of manufacturing the same | Tsai-Jung Ho, Jr-Hung Li, Pei-Yu Chou, Chi-Ta Lee | 2021-11-02 |
| 11164789 | Method for forming semiconductor device that includes covering metal gate with multilayer dielectric | Tsai-Jung Ho, Yu-Shih Wang | 2021-11-02 |
| 11107902 | Dielectric spacer to prevent contacting shorting | Ting-Gang Chen, Tai-Chun Huang, Yi-Ting Fu, Ming-Chang Wen, Shu-Yuan Ku +2 more | 2021-08-31 |
| 11107921 | Source/drain recess in a semiconductor device | Eric Peng, Chao-Cheng Chen, Chii-Horng Li, Ming-Hua Yu, Shih-Hao Lo +2 more | 2021-08-31 |
| 11069528 | Semiconductor device and method | Ching-Yu Chang, Jung-Hau Shiu, Jen Hung Wang | 2021-07-20 |
| 11053584 | System and method for supplying a precursor for an atomic layer deposition (ALD) process | Bor Chiuan Hsieh, Chien-Kuo Huang, Tai-Chun Huang, Kuang-Yuan Hsu | 2021-07-06 |
| 11049763 | Multi-patterning to form vias with straight profiles | Chun-Kai Chen, Jung-Hau Shiu, Chia-Cheng Chou, Chung-Chi Ko, Chih-Hao Chen +1 more | 2021-06-29 |
| 11008654 | Apparatus and method for spatial atomic layer deposition | Anthony Hong Lin, Ching-Lun Lai, Pei-Ren Jeng | 2021-05-18 |
| 10978301 | Morphology of resist mask prior to etching | Ching-Yu Chang, Jung-Hau Shiu, Wei-Ren Wang, Shing-Chyang Pan | 2021-04-13 |
| 10916656 | MOS devices having epitaxy regions with reduced facets | Hsueh-Chang Sung, Kun-Mu Li, Chii-Horng Li, Tsz-Mei Kwok | 2021-02-09 |