Issued Patents 2019
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10516021 | Reduced leakage transistors with germanium-rich channel regions | Glenn A. Glass, Karthik Jambunathan, Anand S. Murthy, Chandra S. Mohapatra, Jun Sung Kang | 2019-12-24 |
| 10483385 | Nanowire structures having wrap-around contacts | Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Michael Haverty, Sadasivan Shankar | 2019-11-19 |
| 10424580 | Semiconductor devices having modulated nanowire counts | Annalisa Cappellani, Kelin J. Kuhn, Rafael Rios, Gopinath Bhimarasetti, Tahir Ghani | 2019-09-24 |
| 10304946 | Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices | Rishabh Mehandru, Patrick Morrow, Ranjith Kumar, Cory E. Weber, Stephen M. Cea +1 more | 2019-05-28 |
| 10283589 | Integration methods to fabricate internal spacers for nanowire devices | Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong, Rafael Rios +2 more | 2019-05-07 |
| 10249742 | Offstate parasitic leakage reduction for tunneling field effect transistors | Van H. Le, Gilbert Dewey, Benjamin Chu-Kung, Ashish Agrawal, Matthew V. Metz +8 more | 2019-04-02 |