Issued Patents 2019
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10461155 | Epitaxial region for embedded source/drain region having uniform thickness | Yoong Hooi Yong, Yanping Shen, Xusheng Wu, Joo Tat Ong, Wei Hong +6 more | 2019-10-29 |
| 10431665 | Multiple-layer spacers for field-effect transistors | Tao Han, Zhenyu Hu, Jinping Liu, Jianwei Peng | 2019-10-01 |
| 10410929 | Multiple gate length device with self-aligned top junction | Hui Zang, Jianwei Peng, Yi Qi, Jerome Ciavatti, Ruilong Xie | 2019-09-10 |
| 10388652 | Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same | Yongiun Shi, Lei Sun, Laertis Economikos, Ruilong Xie, Lars Liebmann +4 more | 2019-08-20 |
| 10355104 | Single-curvature cavity for semiconductor epitaxy | Yi Qi, Sang Woo Lim, Kyung-Bum Koo, Alina Vinslava, Pei Zhao +3 more | 2019-07-16 |
| 10297675 | Dual-curvature cavity for epitaxial semiconductor growth | Alina Vinslava, Yongjun Shi, Jianwei Peng, Jianghu Yan, Yi Qi | 2019-05-21 |
| 10276689 | Method of forming a vertical field effect transistor (VFET) and a VFET structure | Yi Qi, Jianwei Peng, Ruilong Xie, Xunyuan Zhang, Hui Zang | 2019-04-30 |
| 10262903 | Boundary spacer structure and integration | Judson R. Holt, Yi Qi, Jianwei Peng | 2019-04-16 |
| 10249538 | Method of forming vertical field effect transistors with different gate lengths and a resulting structure | Yi Qi, Jianwei Peng, Wei Hong, Yanping Shen, Yongjun Shi +5 more | 2019-04-02 |
| 10211317 | Vertical-transport field-effect transistors with an etched-through source/drain cavity | Yi Qi, Xusheng Wu, Jianwei Peng, Sipeng Gu | 2019-02-19 |