DG

Dechao Guo

IBM: 17 patents #200 of 11,143Top 2%
RE Renesas Electronics: 1 patents #231 of 741Top 35%
Overall (2019): #2,957 of 560,194Top 1%
17
Patents 2019

Issued Patents 2019

Patent #TitleCo-InventorsDate
10510892 Forming a sacrificial liner for dual channel devices Huiming Bu, Kangguo Cheng, Sivananda K. Kanakasabapathy, Peng Xu 2019-12-17
10468412 Formation of a semiconductor device with selective nitride grown on conductor Ruqiang Bao, Zuoguang Liu 2019-11-05
10381479 Interface charge reduction for SiGe surface Devendra K. Sadana, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell, Shogo Mochizuki +3 more 2019-08-13
10361210 Low-drive current FinFET structure for improving circuit density of ratioed logic in SRAM devices Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh 2019-07-23
10355106 Replacement metal gate scheme with self-alignment gate for vertical field effect transistors Raqiang Bao 2019-07-16
10332883 Integrated metal gate CMOS devices Ruqiang Bao, Vijay Narayanan 2019-06-25
10312370 Forming a sacrificial liner for dual channel devices Huiming Bu, Kangguo Cheng, Sivananda K. Kanakasabapathy, Peng Xu 2019-06-04
10263098 Threshold voltage modulation through channel length adjustment Ruqiang Bao, Derrick Liu, Huimei Zhou 2019-04-16
10256238 Preserving channel strain in fin cuts Andrew M. Greene, Ravikumar Ramachandran, Rajasekhar Venigalla 2019-04-09
10256150 Fabricating Fin-based split-gate high-drain-voltage transistor by work function tuning Liyang Song, Xinhui Wang, Qintao Zhang 2019-04-09
10249542 Self-aligned doping in source/drain regions for low contact resistance Zuoguang Liu, Gen Tsutsui, Heng Wu 2019-04-02
10249758 FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation Hemanth Jagannathan, Shogo Mochizuki, Gen Tsutsui, Chun-Chen Yeh 2019-04-02
10249714 Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction Shogo Mochizuki, Andreas Scholze, Chun-Chen Yeh 2019-04-02
10224419 Threshold voltage modulation through channel length adjustment Ruqiang Bao, Derrick Liu, Huimei Zhou 2019-03-05
10211207 Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices Praneet Adusumilli, Oleg Gluschenkov, Zuoguang Liu, Rajasekhar Venigalla, Tenko Yamashita 2019-02-19
10170368 Fabricating fin-based split-gate high-drain-voltage transistor by work function tuning Liyang Song, Xinhui Wang, Qintao Zhang 2019-01-01
10170593 Threshold voltage modulation through channel length adjustment Ruqiang Bao, Derrick Liu, Huimei Zhou 2019-01-01