Issued Patents 2019
Showing 1–25 of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10505016 | Self aligned gate shape preventing void formation | Andrew M. Greene, Qing Liu, Ruilong Xie | 2019-12-10 |
| 10468525 | VFET CMOS dual epitaxy integration | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2019-11-05 |
| 10453939 | Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2019-10-22 |
| 10439031 | Integration of vertical-transport transistors and electrical fuses | Ruilong Xie, Kangguo Cheng, Tenko Yamashita | 2019-10-08 |
| 10431682 | Vertical vacuum channel transistor | Qing Liu, Ruilong Xie | 2019-10-01 |
| 10395995 | Dual liner silicide | Balasubramanian Pranatharthiharan, Ruilong Xie | 2019-08-27 |
| 10396000 | Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions | Tenko Yamashita, Hui Zang | 2019-08-27 |
| 10396183 | Parasitic capacitance reducing contact structure in a finFET | Miaomiao Wang, Tenko Yamashita, Hui Zang | 2019-08-27 |
| 10396208 | Vertical transistors with improved top source/drain junctions | Kangguo Cheng, Muthumanickam Sankarapandian, Ruilong Xie, Tenko Yamashita | 2019-08-27 |
| 10388769 | Parasitic capacitance reducing contact structure in a finFET | Miaomiao Wang, Tenko Yamashita, Hui Zang | 2019-08-20 |
| 10388768 | Parasitic capacitance reducing contact structure in a finFET | Miaomiao Wang, Tenko Yamashita, Hui Zang | 2019-08-20 |
| 10381273 | Vertically stacked multi-channel transistor structure | Kangguo Cheng, Tenko Yamashita, Ruilong Xie | 2019-08-13 |
| 10381442 | Low resistance source drain contact formation | Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi | 2019-08-13 |
| 10367069 | Fabrication of vertical field effect transistor structure with controlled gate length | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2019-07-30 |
| 10361210 | Low-drive current FinFET structure for improving circuit density of ratioed logic in SRAM devices | Veeraraghavan S. Basker, Dechao Guo, Zuoguang Liu, Tenko Yamashita | 2019-07-23 |
| 10361315 | Method and apparatus of fabricating source and drain epitaxy for vertical field effect transistor | Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Cheng Chi, Chen Zhang | 2019-07-23 |
| 10355086 | High doped III-V source/drain junctions for field effect transistors | Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie | 2019-07-16 |
| 10355020 | FinFETs having strained channels, and methods of fabricating finFETs having strained channels | Qing Liu, Xiuyu Cai, Ruilong Xie | 2019-07-16 |
| 10347719 | Nanosheet transistors on bulk material | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2019-07-09 |
| 10347739 | Extended contact area using undercut silicide extensions | Effendi Leobandung, Soon-Cheon Seo, Tenko Yamashita | 2019-07-09 |
| 10340362 | Spacers for tight gate pitches in field effect transistors | Ruilong Xie | 2019-07-02 |
| 10332961 | Inner spacer for nanosheet transistors | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2019-06-25 |
| 10319731 | Integrated circuit structure having VFET and embedded memory structure and method of forming same | Ruilong Xie, Tenko Yamashita, Kangguo Cheng | 2019-06-11 |
| 10319840 | Fin field effect transistor fabrication and devices having inverted T-shaped gate | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2019-06-11 |
| 10312377 | Localized fin width scaling using a hydrogen anneal | Veeraraghavan S. Basker, Shogo Mochizuki, Tenko Yamashita | 2019-06-04 |