Issued Patents 2018
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10141405 | Lateral bipolar junction transistor with abrupt junction and compound buried oxide | Pouya Hashemi, Tak H. Ning, Alexander Reznicek | 2018-11-27 |
| 10128343 | III-V MOSFET with self-aligned diffusion barrier | Cheng-Wei Cheng, Jack O. Chu, Yanning Sun, Jeng-Bang Yau | 2018-11-13 |
| 10079278 | Bipolar transistor with carbon alloyed contacts | Bahman Hekmatshoartabari, Tak H. Ning | 2018-09-18 |
| 10074734 | Germanium lateral bipolar transistor with silicon passivation | Tak H. Ning, Jeng-Bang Yau | 2018-09-11 |
| 10068967 | Self-forming spacers using oxidation | Masaharu Kobayashi, Effendi Leobandung | 2018-09-04 |
| 10050039 | Semiconductor structures with deep trench capacitor and methods of manufacture | Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodorus E. Standaert +1 more | 2018-08-14 |
| 10043711 | Contact resistance reduction by III-V Ga deficient surface | Takashi Ando, John Rozen, Jeng-Bang Yau, Yu Zhu | 2018-08-07 |
| 10042968 | Semiconductor structures with deep trench capacitor and methods of manufacture | Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodorus E. Standaert +1 more | 2018-08-07 |
| 9947755 | III-V MOSFET with self-aligned diffusion barrier | Cheng-Wei Cheng, Jack O. Chu, Yanning Sun, Jeng-Bang Yau | 2018-04-17 |
| 9947677 | High-density EEPROM arrays having parallel-connected common-floating-gate NFET and PFET as memory cell | Bahman Hekmatshoartabari, Tak H. Ning, Jeng-Bang Yau | 2018-04-17 |
| 9887278 | Semiconductor-on-insulator lateral heterojunction bipolar transistor having epitaxially grown intrinsic base and deposited extrinsic base | Jin Cai, Christopher P. D'Emic, Tak H. Ning, Jeng-Bang Yau | 2018-02-06 |
| 9865737 | Formation of FinFET junction | Pouya Hashemi, Ali Khakifirooz, John A. Ott, Alexander Reznicek | 2018-01-09 |