| 10103068 |
Detecting a void between a via and a wiring line |
Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon |
2018-10-16 |
| 10049974 |
Metal silicate spacers for fully aligned vias |
Benjamin D. Briggs, Jessica Dechene, Joe Lee |
2018-08-14 |
| 10002831 |
Selective and non-selective barrier layer wet removal |
Benjamin D. Briggs, Raghuveer R. Patlolla, Cornelius Brown Peethala, David L. Rath, Hosadurga Shobha |
2018-06-19 |
| 9960117 |
Air gap semiconductor structure with selective cap bilayer |
Stephen M. Gates, Dimitri Kioussis, Christopher J. Penny, Deepika Priyadarshini |
2018-05-01 |
| 9911690 |
Interconnect structures with fully aligned vias |
Daniel C. Edelstein, Nicholas C. M. Fuller, Satyanarayana V. Nitta, David L. Rath |
2018-03-06 |
| 9905513 |
Selective blocking boundary placement for circuit locations requiring electromigration short-length |
Benjamin D. Briggs, Joe Lee, Christopher J. Penny |
2018-02-27 |
| 9881833 |
Barrier planarization for interconnect metallization |
Benjamin D. Briggs, Takeshi Nogami, Raghuveer R. Patlolla, Cornelius Brown Peethala, David L. Rath |
2018-01-30 |
