Issued Patents 2017
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9842804 | Methods for reducing dual damascene distortion | Chao-Chun Wang, Po-Cheng Shih | 2017-12-12 |
| 9818638 | Manufacturing method of semiconductor device | Yu-Yun Peng, Shing-Chyang Pan | 2017-11-14 |
| 9768061 | Low-k dielectric interconnect systems | Po-Cheng Shih, Chia-Cheng Chou | 2017-09-19 |
| 9754818 | Via patterning using multiple photo multiple etch | Jung-Hau Shiu, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng | 2017-09-05 |
| 9754822 | Interconnect structure and method | Chia-Cheng Chou, Chih-Chien Chi, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo +3 more | 2017-09-05 |
| 9679804 | Multi-patterning to form vias with straight profiles | Chun-Kai Chen, Jung-Hau Shiu, Chia-Cheng Chou, Tze-Liang Lee, Chih-Hao Chen +1 more | 2017-06-13 |
| 9679848 | Interconnect structure for semiconductor devices | Han-Hsin Kuo, Neng-Jye Yang, Fu-Ming Huang, Chi-Ming Tsai, Liang-Guang Chen | 2017-06-13 |
| 9659811 | Manufacturing method of semiconductor device | Yu-Yun Peng, Shing-Chyang Pan | 2017-05-23 |
| 9640428 | Self-aligned repairing process for barrier layer | Chih-Chien Chi, Mei-Ling Chen, Huang-Yi Huang, Szu-Ping Tung, Ching-Hua Hsieh | 2017-05-02 |
| 9589856 | Automatically adjusting baking process for low-k dielectric material | Chia-Cheng Chou, Keng-Chu Lin, Shwang-Ming Jeng | 2017-03-07 |