Issued Patents 2017
Showing 26–50 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9716367 | Semiconductor optoelectronics and CMOS on sapphire substrate | Tymon Barwicz, Ning Li, Jean-Olivier Plouchart, Devendra K. Sadana | 2017-07-25 |
| 9716160 | Extended contact area using undercut silicide extensions | Soon-Cheon Seo, Tenko Yamashita, Chun-Chen Yeh | 2017-07-25 |
| 9716030 | Aspect ratio for semiconductor on insulator | — | 2017-07-25 |
| 9711648 | Structure and method for CMP-free III-V isolation | Chung-Hsun Lin, Amlan Majumdar, Yanning Sun | 2017-07-18 |
| 9711617 | Dual isolation fin and method of making | Cheng-Wei Cheng, Sanghoon Lee | 2017-07-18 |
| 9704950 | Method to form SOI fins on a bulk substrate with suspended anchoring | — | 2017-07-11 |
| 9704866 | Integrated circuit having dual material CMOS integration and method to fabricate same | — | 2017-07-11 |
| 9698239 | Growing groups III-V lateral nanowire channels | Sanghoon Lee, Renee T. Mo, Brent A. Wacaser | 2017-07-04 |
| 9698225 | Localized and self-aligned punch through stopper doping for finFET | Tenko Yamashita | 2017-07-04 |
| 9691709 | Semiconductor device security | — | 2017-06-27 |
| 9687181 | Semiconductor device to be embedded within a contact lens | Ghavam G. Shahidi | 2017-06-27 |
| 9685410 | Semiconductor device security | — | 2017-06-20 |
| 9685329 | Embedded gallium-nitride in silicon | William J. Gallagher, Devendra K. Sadana, Ghavam G. Shahidi | 2017-06-20 |
| 9685501 | Low parasitic capacitance finFET device | — | 2017-06-20 |
| 9685521 | Lowering parasitic capacitance of replacement metal gate processes | Vijay Narayanan | 2017-06-20 |
| 9679775 | Selective dopant junction for a group III-V semiconductor device | Kevin K. Chan, Marinus Hopstaken, Young-Hee Kim, Masaharu Kobayashi, Deborah A. Neumayer +3 more | 2017-06-13 |
| 9673056 | Method to improve finFET cut overlay | Tenko Yamashita | 2017-06-06 |
| 9666748 | Integrated on chip detector and zero waveguide module structure for use in DNA sequencing | — | 2017-05-30 |
| 9660069 | Group III nitride integration with CMOS technology | Can Bayram, Christopher P. D'Emic, William J. Gallagher, Devendra K. Sadana | 2017-05-23 |
| 9653464 | Asymmetric band gap junctions in narrow band gap MOSFET | — | 2017-05-16 |
| 9653347 | Vertical air gap subtractive etch back end metal | — | 2017-05-16 |
| 9647091 | Annealed metal source drain overlapping the gate | — | 2017-05-09 |
| 9640536 | Method to make dual material finFET on same substrate | — | 2017-05-02 |
| 9640442 | CMOS fin integration on SOI substrate | Tenko Yamashita | 2017-05-02 |
| 9627266 | Dual-semiconductor complementary metal-oxide-semiconductor device | Sanghoon Lee, Renee T. Mo, Yanning Sun | 2017-04-18 |