Issued Patents 2017
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9806195 | Method for fabricating transistor with thinned channel | Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle +3 more | 2017-10-31 |
| 9773903 | Asymmetric III-V MOSFET on silicon substrate | Cheng-Wei Cheng, Pranita Kerber, Effendi Leobandung, Renee T. Mo, Yanning Sun | 2017-09-26 |
| 9761724 | Semiconductor device structures and methods of forming semiconductor structures | Justin K. Brask, Jack T. Kavalieros, Brian S. Doyle, Uday Shah, Suman Datta +1 more | 2017-09-12 |
| 9748357 | III-V MOSFET with strained channel and semi-insulating bottom barrier | Anirban Basu, Guy M. Cohen | 2017-08-29 |
| 9711648 | Structure and method for CMP-free III-V isolation | Effendi Leobandung, Chung-Hsun Lin, Yanning Sun | 2017-07-18 |
| 9704958 | III-V field effect transistor on a dielectric layer | Cheng-Wei Cheng, Edward W. Kiewra, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun | 2017-07-11 |
| 9691856 | Extreme high mobility CMOS logic | Suman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Justin K. Brask +3 more | 2017-06-27 |
| 9666684 | III-V semiconductor device having self-aligned contacts | Anirban Basu, Yanning Sun | 2017-05-30 |
| 9653606 | Fabrication process for mitigating external resistance of a multigate device | Anirban Basu, Guy M. Cohen | 2017-05-16 |
| 9564514 | Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels | Anirban Basu, Jeffrey W. Sleight | 2017-02-07 |
| 9553166 | Asymmetric III-V MOSFET on silicon substrate | Cheng-Wei Cheng, Pranita Kerber, Effendi Leobandung, Renee T. Mo, Yanning Sun | 2017-01-24 |