Issued Patents 2016
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9490197 | Three dimensional organic or glass interposer | Mukta G. Farooq, William Francis Landers, Andrew J. Martin, Kathryn E. Schlichting, Melissa A. Smith | 2016-11-08 |
| 9472465 | Methods of fabricating integrated circuits | Bongki Lee, Bharat Krishnan | 2016-10-18 |
| 9466723 | Liner and cap layer for placeholder source/drain contact structure planarization and replacement | Haigou Huang, Qiang Fang, Huang Liu | 2016-10-11 |
| 9455201 | Integration method for fabrication of metal gate based multiple threshold voltage devices and circuits | Manoj Joshi, Manfred Eller, Rohit Pal, Richard J. Carter, Srikanth B. Samavedam +1 more | 2016-09-27 |
| 9443956 | Method for forming air gap structure using carbon-containing spacer | Hong Yu, Biao Zuo, Huang Liu | 2016-09-13 |
| 9419126 | Integrated circuits and methods for fabricating integrated circuits with active area protection | Xiaodong Yang, Yanxiang Liu, Xusheng Wu | 2016-08-16 |
| 9406676 | Method for forming single diffusion breaks between finFET devices and the resulting devices | Hong Yu, Hongliang Shen, Zhenyu Hu | 2016-08-02 |
| 9401416 | Method for reducing gate height variation due to overlapping masks | Hong Yu, Haigou Huang, Huang Liu | 2016-07-26 |
| 9373535 | T-shaped fin isolation region and methods of fabrication | Hongliang Shen, Zhenyu Hu | 2016-06-21 |
| 9366865 | Wearable electronic device with integrated antenna | Liefeng Jin, Jinqiang Lin | 2016-06-14 |
| 9368342 | Defect-free relaxed covering layer on semiconductor substrate with lattice mismatch | Haigou Huang, Huang Liu | 2016-06-14 |
| 9362180 | Integrated circuit having multiple threshold voltages | Bongki Lee, Manoj Joshi, Manfred Eller, Rohit Pal, Richard J. Carter +1 more | 2016-06-07 |
| 9343371 | Fabricating fin structures with doped middle portions | Xusheng Wu | 2016-05-17 |
| 9312145 | Conformal nitridation of one or more fin-type transistor layers | Wei Tong, Tien Ying Luo, Yan Ping SHEN, Feng Zhou, Jun Lian +4 more | 2016-04-12 |
| 9293382 | Voltage contrast inspection of deep trench isolation | Norbert Arnold, Brian W. Messenger, Oliver D. Patterson | 2016-03-22 |
| 9263520 | Facilitating fabricating gate-all-around nanowire field-effect transistors | Jing Wan, Andy Wei | 2016-02-16 |
| 9236481 | Semiconductor device and methods of forming fins and gates with ultraviolet curing | Hui Zang | 2016-01-12 |
| 9230822 | Uniform gate height for mixed-type non-planar semiconductor devices | Hong Yu, Haigou Huang, Huang Liu | 2016-01-05 |