Issued Patents 2016
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9520395 | FinFET devices comprising a dielectric layer/CMP stop layer/hardmask/etch stop layer/gap-fill material stack | Guillaume Bouche, Xiang Hu, Jerome F. Wandell, Sandeep Gaan | 2016-12-13 |
| 9515026 | Methods of forming alignment marks and overlay marks on integrated circuit products employing FinFET devices and the resulting alignment/overlay mark | Jeong Soo Kim, Francis M. Tambwe | 2016-12-06 |
| 9508850 | Epitaxial block layer for a fin field effect transistor device | Zhenyu Hu, Richard J. Carter, Qi Zhang, Sruthi Muralidharan, Amy L. Child | 2016-11-29 |
| 9508642 | Self-aligned back end of line cut | Guillaume Bouche, Mark A. Zaleski | 2016-11-29 |
| 9502293 | Self-aligned via process flow | Guillaume Bouche, Sudharshanan Raghunthathan | 2016-11-22 |
| 9502528 | Borderless contact formation through metal-recess dual cap integration | Guillaume Bouche, Jason E. Stephens, Tuhin Guha Neogi, Mark A. Zaleski | 2016-11-22 |
| 9490340 | Methods of forming nanowire devices with doped extension regions and the resulting devices | Shao-Ming Koh, Guillaume Bouche, Jing Wan | 2016-11-08 |
| 9461128 | Method for creating self-aligned transistor contacts | Mark A. Zaleski, Jason E. Stephens, Tuhin Guha Neogi, Guillaume Bouche | 2016-10-04 |
| 9455316 | Three-dimensional electrostatic discharge semiconductor device | Jagar Singh, Mahadeva Iyer Natarajan | 2016-09-27 |
| 9450073 | SOI transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto | Thorsten Kammler, Roman Boschke, Casey Scott | 2016-09-20 |
| 9449826 | Graded well implantation for asymmetric transistors having reduced gate electrode pitches | G Robert Mulfinger, Jan Hoentschel, Vassilios Papageorgiou | 2016-09-20 |
| 9437713 | Devices and methods of forming higher tunability FinFET varactor | Jagar Singh, Gopal Srinivasan, Amaury Gendron | 2016-09-06 |
| 9431512 | Methods of forming nanowire devices with spacers and the resulting devices | Shao-Ming Koh, Guillaume Bouche, Jing Wan | 2016-08-30 |
| 9425097 | Cut first alternative for 2D self-aligned via | Guillaume Bouche, Sudharshanan Raghunathan | 2016-08-23 |
| 9412655 | Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines | Guillaume Bouche, Jason E. Stephens, Vikrant Chauhan | 2016-08-09 |
| 9406775 | Method for creating self-aligned compact contacts in an IC device meeting fabrication spacing constraints | Guillaume Bouche, Youngtag Woo | 2016-08-02 |
| 9397004 | Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openings | Guillaume Bouche, Erik Geiss, Scott Beasor, Deniz E. Civay | 2016-07-19 |
| 9390979 | Opposite polarity borderless replacement metal contact scheme | Guillaume Bouche, Huy Cao, Jing Wan | 2016-07-12 |
| 9368395 | Self-aligned via and air gap | Mark A. Zaleski | 2016-06-14 |
| 9362279 | Contact formation for semiconductor device | Ruilong Xie, William J. Taylor, Jr., Ryan Ryoung-Han Kim, Kwan-Yong Lim, Chanro Park | 2016-06-07 |
| 9362165 | 2D self-aligned via first process flow | Guillaume Bouche, Sudharshanan Raghunathan | 2016-06-07 |
| 9349718 | ESD snapback based clamp for finFET | Jagar Singh, Mahadeva Iyer Natarajan, Manjunatha Prabhu, Anil Kumar | 2016-05-24 |
| 9343456 | Metal gate for robust ESD protection | Amaury Gendron-Hansen, Jagar Singh | 2016-05-17 |
| 9306019 | Integrated circuits with nanowires and methods of manufacturing the same | Jing Wan, Guillaume Bouche, Shao-Ming Koh | 2016-04-05 |
| 9305785 | Semiconductor contacts and methods of fabrication | Guillaume Bouche, Gabriel Padron Wells, Xiang Hu | 2016-04-05 |