Issued Patents 2016
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9502564 | Fully depleted device with buried insulating layer in channel region | Hans-Peter Moll, Peter Baars | 2016-11-22 |
| 9490344 | Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process | Stefan Flachowsky, Thilo Scheiper | 2016-11-08 |
| 9490189 | Semiconductor device comprising a stacked die configuration including an integrated peltier element | Uwe Griebenow, Thilo Scheiper, Sven Beyer | 2016-11-08 |
| 9472642 | Method of forming a semiconductor device structure and such a semiconductor device structure | Stefan Flachowsky, Ralf Richter, Peter Javorka | 2016-10-18 |
| 9466717 | Complex semiconductor devices of the SOI type | Ran Yan, Alban Zaka | 2016-10-11 |
| 9461145 | OPC enlarged dummy electrode to eliminate ski slope at eSiGe | Ran Yan, Martin Gerhardt | 2016-10-04 |
| 9449972 | Ferroelectric FinFET | Stefan Flachowsky, Ralf Illgen | 2016-09-20 |
| 9449826 | Graded well implantation for asymmetric transistors having reduced gate electrode pitches | G Robert Mulfinger, Andy Wei, Vassilios Papageorgiou | 2016-09-20 |
| 9443871 | Cointegration of bulk and SOI semiconductor devices | Peter Baars, Hans-Peter Moll | 2016-09-13 |
| 9443945 | Transistor including a gate electrode extending all around one or more channel regions | Stefan Flachowsky | 2016-09-13 |
| 9431508 | Simplified gate-first HKMG manufacturing flow | Stefan Flachowsky, Roman Boschke | 2016-08-30 |
| 9425318 | Integrated circuits with fets having nanowires and methods of manufacturing the same | Stefan Flachowsky, Gerd Zschaetzsch | 2016-08-23 |
| 9425052 | Reduced threshold voltage-width dependency in transistors comprising high-K metal gate electrode structures | Thilo Scheiper, Steven Langdon | 2016-08-23 |
| 9412848 | Methods of forming a complex GAA FET device at advanced technology nodes | Ralf Richter, Peter Javorka, Stefan Flachowsky | 2016-08-09 |
| 9412859 | Contact geometry having a gate silicon length decoupled from a transistor length | Ralf Richter, Peter Javorka, Stefan Flachowsky | 2016-08-09 |
| 9406565 | Methods for fabricating integrated circuits with semiconductor substrate protection | Peter Javorka, Ralf Richter | 2016-08-02 |
| 9396950 | Low thermal budget schemes in semiconductor device fabrication | Nicolas Sassiat, Torben Balzer, Alban Zaka | 2016-07-19 |
| 9391176 | Multi-gate FETs having corrugated semiconductor stacks and method of forming the same | Stefan Flachowsky, Ralf Richter, Peter Javorka | 2016-07-12 |
| 9391156 | Embedded capacitor | Hans-Peter Moll, Peter Baars | 2016-07-12 |
| 9385232 | FD devices in advanced semiconductor techniques | Hans-Peter Moll, Peter Baars | 2016-07-05 |
| 9373509 | FINFET doping method with curvilnear trajectory implantation beam path | Ralf Richter, Stefan Flachowsky, Peter Javorka | 2016-06-21 |
| 9373720 | Three-dimensional transistor with improved channel mobility | Stefan Flachowsky, Ralf Richter, Peter Javorka | 2016-06-21 |
| 9343374 | Efficient main spacer pull back process for advanced VLSI CMOS technologies | Peter Javorka, Stefan Flachowsky, Ralf Richter | 2016-05-17 |
| 9324869 | Method of forming a semiconductor device and resulting semiconductor devices | Ran Yan, Alban Zaka | 2016-04-26 |
| 9324868 | Epitaxial growth of silicon for FinFETS with non-rectangular cross-sections | Ran Yan, Ralf Richter, Hans-Jürgen Thees | 2016-04-26 |