Issued Patents 2016
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9472642 | Method of forming a semiconductor device structure and such a semiconductor device structure | Jan Hoentschel, Stefan Flachowsky, Peter Javorka | 2016-10-18 |
| 9412859 | Contact geometry having a gate silicon length decoupled from a transistor length | Peter Javorka, Jan Hoentschel, Stefan Flachowsky | 2016-08-09 |
| 9412848 | Methods of forming a complex GAA FET device at advanced technology nodes | Peter Javorka, Jan Hoentschel, Stefan Flachowsky | 2016-08-09 |
| 9406565 | Methods for fabricating integrated circuits with semiconductor substrate protection | Peter Javorka, Jan Hoentschel | 2016-08-02 |
| 9391176 | Multi-gate FETs having corrugated semiconductor stacks and method of forming the same | Stefan Flachowsky, Jan Hoentschel, Peter Javorka | 2016-07-12 |
| 9373720 | Three-dimensional transistor with improved channel mobility | Stefan Flachowsky, Jan Hoentschel, Peter Javorka | 2016-06-21 |
| 9373509 | FINFET doping method with curvilnear trajectory implantation beam path | Stefan Flachowsky, Peter Javorka, Jan Hoentschel | 2016-06-21 |
| 9343374 | Efficient main spacer pull back process for advanced VLSI CMOS technologies | Jan Hoentschel, Peter Javorka, Stefan Flachowsky | 2016-05-17 |
| 9324868 | Epitaxial growth of silicon for FinFETS with non-rectangular cross-sections | Ran Yan, Jan Hoentschel, Hans-Jürgen Thees | 2016-04-26 |
| 9318345 | Enhancing transistor performance by reducing exposure to oxygen plasma in a dual stress liner approach | Ronald G. Naumann, Volker Grimm, Andrey Zakharov | 2016-04-19 |
| 9231045 | Methods for fabricating integrated circuits with polycrystalline silicon resistor structures using a replacment gate process flow, and the integrated circuits fabricated thereby | Jan Hoentschel, Stefan Flachowsky, Nicolas Sassiat | 2016-01-05 |