CY

Chen-Hua Yu

TSMC: 14 patents #3 of 898Top 1%
📍 Hsinchu, TW: #1 of 1 inventorsTop 100%
Overall (2004): #529 of 270,089Top 1%
15
Patents 2004

Issued Patents 2004

Showing 1–15 of 15 patents

Patent #TitleCo-InventorsDate
6821905 Method for avoiding carbon and nitrogen contamination of a dielectric insulating layer Shing-Chyang Pan, Shwang-Ming Jeng, Grace H. Ho 2004-11-23
6811670 Method for forming cathode contact areas for an electroplating process Chung-Shi Liu 2004-11-02
6767833 Method for damascene reworking Tsu Shih 2004-07-27
6764959 Thermal compensation method for forming semiconductor integrated circuit microelectronic fabrication Mo Yu, Shih-Chang Chen 2004-07-20
6753259 Method of improving the bondability between Au wires and Cu bonding pads Syun-Ming Jang, Mong-Song Liang, Chung-Shi Liu, Jane-Bai Lai 2004-06-22
6734053 Effective MIM fabrication method and apparatus to avoid breakdown and leakage on damascene copper process Chung-Shi Liu 2004-05-11
6734101 Solution to the problem of copper hillocks Tien-I Bao, Jeng Shwang-Ming, Syun-Ming Jang, Kuen-Chyr Lee 2004-05-11
6734110 Damascene method employing composite etch stop layer Syun-Ming Jang, Chung-Shi Liu 2004-05-11
6726535 Method for preventing localized Cu corrosion during CMP Tsu Shih, Kuan-Ku Hung 2004-04-27
6706637 Dual damascene aperture formation method absent intermediate etch stop layer Yu-Huei Chen, Yao-Yi Cheng, Sung-Ming Jang 2004-03-16
6706577 Formation of dual gate oxide by two-step wet oxidation Jih-Churng Twu, Syun-Ming Jang 2004-03-16
6703286 Metal bond pad for low-k inter metal dielectric Chung-Shi Liu 2004-03-09
6686280 Sidewall coverage for copper damascene filling Shau-Lin Shue, Mei-Yun Wang 2004-02-03
6682396 Apparatus and method for linear polishing Tsu Shih 2004-01-27
6672941 Method and apparatus for chemical/mechanical planarization (CMP) of a semiconductor substrate having shallow trench isolation Syun-Ming Jang 2004-01-06