Issued Patents 2004
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6830996 | Device performance improvement by heavily doped pre-gate and post polysilicon gate clean | Chia-Lin Chen, Tze-Liang Lee | 2004-12-14 |
| 6780741 | Method of forming a novel gate electrode structure comprised of a silicon-germanium layer located between random grained polysilicon layers | Chia-Lin Chen, Liang-Gi Yao | 2004-08-24 |
| 6780788 | Methods for improving within-wafer uniformity of gate oxide | Chi-Chun Chen, Ming-Fang Wang | 2004-08-24 |
| 6767274 | Method to reduce defect/slurry residue for copper CMP | Chi-Chun Chen, Weng Chang | 2004-07-27 |
| 6767847 | Method of forming a silicon nitride-silicon dioxide gate stack | Chien-Ming Hu, Chien-Hao Chen, Mo Yu, Mong-Song Liang | 2004-07-27 |
| 6764927 | Chemical vapor deposition (CVD) method employing wetting pre-treatment | Liang-Gi Yao, Ming-Fang Wang, Yeou-Ming Lin, Tuo-Hung Ho | 2004-07-20 |
| 6764959 | Thermal compensation method for forming semiconductor integrated circuit microelectronic fabrication | Mo Yu, Chen-Hua Yu | 2004-07-20 |
| 6737362 | Method for manufacturing a thin gate dielectric layer for integrated circuit fabrication | Chia-Lin Chen, Chun-Lin Wu, Chi-Chun Chen, Tze-Liang Lee | 2004-05-18 |
| 6727134 | Method of forming a nitride gate dielectric layer for advanced CMOS devices | Chi-Chun Chen, Tze-Liang Lee | 2004-04-27 |
| 6706581 | Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices | Tou-Hung Hou, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Liang-Gi Yao | 2004-03-16 |