Issued Patents 2003
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6670263 | Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size | Arne Ballantine, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles, James J. Quinlivan +3 more | 2003-12-30 |
| 6660598 | Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region | Hussein I. Hanafi, Diane C. Boyd, Wesley C. Natzle, Leathen Shi | 2003-12-09 |
| 6645861 | Self-aligned silicide process for silicon sidewall source and drain contacts | Cyril Cabral, Jr., Guy M. Cohen, Kathryn Guarini, Christian Lavoie, Paul M. Solomon +1 more | 2003-11-11 |
| 6580132 | Damascene double-gate FET | Erin C. Jones, Paul M. Solomon, Hon-Sum Philip Wong | 2003-06-17 |
| 6579614 | Structure having refractory metal film on a substrate | Erin C. Jones, Fenton R. McFeely, Paul M. Solomon, John J. Yurkas | 2003-06-17 |
| 6555880 | Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby | Cyril Cabral, Jr., Guy M. Cohen, Kathryn Guarini, Christian Lavoie, Ronnen Andrew Roy +1 more | 2003-04-29 |
| 6544874 | Method for forming junction on insulator (JOI) structure | Jack A. Mandelman, Bomy Chen, Oleg Gluschenkov, Rajarao Jammy, Victor Ku +2 more | 2003-04-08 |
| 6503833 | Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby | Atul Ajmera, Cyril Cabral, Jr., Roy A. Carruthers, Guy M. Cohen, Paul Kozlowski +3 more | 2003-01-07 |