Issued Patents 2003
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6664598 | Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control | Robert H. Dennard, Wilfried E. Haensch | 2003-12-16 |
| 6660598 | Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region | Diane C. Boyd, Kevin K. Chan, Wesley C. Natzle, Leathen Shi | 2003-12-09 |
| 6656824 | Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch | Wesley C. Natzle | 2003-12-02 |
| 6635923 | Damascene double-gate MOSFET with vertical channel regions | Jeffrey J. Brown, Wesley C. Natzle | 2003-10-21 |
| 6593617 | Field effect transistors with vertical gate side walls and method for making such transistors | Diane C. Boyd, Stuart M. Burns, Yuan Taur, William C. Wille | 2003-07-15 |
| 6562713 | Method of protecting semiconductor areas while exposing a gate | Michael P. Belyansky, Omer H. Dokumaci, Bruce B. Doris | 2003-05-13 |