Issued Patents 2003
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6660598 | Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region | Hussein I. Hanafi, Diane C. Boyd, Kevin K. Chan, Leathen Shi | 2003-12-09 |
| 6656824 | Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch | Hussein I. Hanafi | 2003-12-02 |
| 6635923 | Damascene double-gate MOSFET with vertical channel regions | Hussein I. Hanafi, Jeffrey J. Brown | 2003-10-21 |
| 6617085 | Wet etch reduction of gate widths | Babar A. Kanh, Naim Moumen, Chienfan Yu | 2003-09-09 |