AA

Atul Ajmera

IBM: 8 patents #106 of 5,539Top 2%
KT Kabushiki Kaisha Toshiba: 1 patents #624 of 1,928Top 35%
📍 Poughkeepsie, NY: #3 of 210 inventorsTop 2%
🗺 New York: #134 of 9,423 inventorsTop 2%
Overall (2003): #3,336 of 273,478Top 2%
8
Patents 2003

Issued Patents 2003

Showing 1–8 of 8 patents

Patent #TitleCo-InventorsDate
6642156 Method for forming heavy nitrogen-doped ultra thin oxynitride gate dielectrics Evgeni Gousev, Christopher P. D'Emic 2003-11-04
6605521 Method of forming an oxide film on a gate side wall of a gate structure Karanam Balasubramanyam, Tomio Katata, Shang-Bin Ko 2003-08-12
6602759 Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysilicon Klaus D. Beyer, Dominic J. Schepis 2003-08-05
6566210 Method of improving gate activation by employing atomic oxygen enhanced oxidation Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov 2003-05-20
6566198 CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufacture Heemyong Park, Fariborz Assaderaghi, Ghavam G. Shahidi 2003-05-20
6521947 Method of integrating substrate contact on SOI wafers with STI process Effendi Leobandung, Werner Rausch, Dominic J. Schepis, Ghavam G. Shahidi 2003-02-18
6506649 Method for forming notch gate having self-aligned raised source/drain structure Ka-Hing Fung, Victor Ku, Dominic J. Schepis 2003-01-14
6503833 Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby Cyril Cabral, Jr., Roy A. Carruthers, Kevin K. Chan, Guy M. Cohen, Paul Kozlowski +3 more 2003-01-07