Issued Patents 2003
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6627511 | Reduced stress isolation for SOI devices and a method for fabricating | Marco Racanelli, Hyungcheol Shin | 2003-09-30 |
| 6566198 | CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufacture | Fariborz Assaderaghi, Atul Ajmera, Ghavam G. Shahidi | 2003-05-20 |
| 6562666 | Integrated circuits with reduced substrate capacitance | Fariborz Assaderaghi, Jack A. Mandelman, Ghavam G. Shahidi, Lawrence F. Wagner, Jr. | 2003-05-13 |
| 6509241 | Process for fabricating an MOS device having highly-localized halo regions | Anda C. Mocuta, Paul A. Ronsheim | 2003-01-21 |