Issued Patents 2003
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6657261 | Ground-plane device with back oxide topography | Fariborz Assaderaghi, Tze-Chiang Chen, K. Paul Muller, Edward J. Nowak, Devendra K. Sadana | 2003-12-02 |
| 6653698 | Integration of dual workfunction metal gate CMOS devices | Byoung Hun Lee, Effendi Leobandung | 2003-11-25 |
| 6645795 | Polysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator | K. Paul Muller, Dominic J. Schepis | 2003-11-11 |
| 6635517 | Use of disposable spacer to introduce gettering in SOI layer | Tze-Chiang Chen, Thomas T. Hwang, Mukesh V. Khare, Effendi Leobandung, Anda C. Mocuta +1 more | 2003-10-21 |
| 6566198 | CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufacture | Heemyong Park, Fariborz Assaderaghi, Atul Ajmera | 2003-05-20 |
| 6566177 | Silicon-on-insulator vertical array device trench capacitor DRAM | Carl Radens, Gary B. Bronner, Tze-Chiang Chen, Bijan Davari, Jack A. Mandelman +3 more | 2003-05-20 |
| 6562666 | Integrated circuits with reduced substrate capacitance | Heemyong Park, Fariborz Assaderaghi, Jack A. Mandelman, Lawrence F. Wagner, Jr. | 2003-05-13 |
| 6541317 | Polysilicon doped transistor | K. Paul Muller, Dominic J. Schepis | 2003-04-01 |
| 6521947 | Method of integrating substrate contact on SOI wafers with STI process | Atul Ajmera, Effendi Leobandung, Werner Rausch, Dominic J. Schepis | 2003-02-18 |
| 6521949 | SOI transistor with polysilicon seed | Fariborz Assaderaghi, Tze-Chiang Chen, K. Paul Muller, Edward J. Nowak | 2003-02-18 |