Issued Patents 2002
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6492242 | Method of forming of high K metallic dielectric layer | Cher Liang Cha, Shyuz Fong Quek, Ting Cheong Ang, Wye Boon Loh, Sang Yee Loong +2 more | 2002-12-10 |
| 6475875 | Shallow trench isolation elevation uniformity via insertion of a polysilicon etch layer | Pang Chong Hau, Chen Feng, Peter Hing | 2002-11-05 |
| 6472697 | Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application | Yeow Kheng Lim, Randall Cher Liang Cha, Wang Ling Goh, Victor Lim | 2002-10-29 |
| 6468880 | Method for fabricating complementary silicon on insulator devices using wafer bonding | Yeow Kheng Lim, Randall Cher Liang Cha, Tae Jong Lee, Wang Ling Goh | 2002-10-22 |
| 6436833 | Method for pre-STI-CMP planarization using poly-si thermal oxidation | Chong Hau Pang, Chen Feng, Peter Hing | 2002-08-20 |
| 6432797 | Simplified method to reduce or eliminate STI oxide divots | Randall Cher Liang Cha, Tae Jong Lee, Lap Chan, Yeow Kheng Lim | 2002-08-13 |
| 6399471 | Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application | Yeow Kheng Lim, Randall Cher Liang Cha, Wang Ling Goh, Victor Lim | 2002-06-04 |
| 6391731 | Activating source and drain junctions and extensions using a single laser anneal | Yung Fu Chong, Kin Leong Pey | 2002-05-21 |
| 6391720 | Process flow for a performance enhanced MOSFET with self-aligned, recessed channel | Sneedharan Pillai Sneelal, Francis Poh, James Yong Meng Lee, C. K. Lau, Ganesh Samudra | 2002-05-21 |
| 6387747 | Method to fabricate RF inductors with minimum area | Randall Cher Liang Cha, Tae Jong Lee, Lap Chan, Chua Chee Tee | 2002-05-14 |
| 6380066 | Methods for eliminating metal corrosion by FSG | Kok Hin Teo, Kok Hiang Tang | 2002-04-30 |
| 6365446 | Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process | Yung Fu Chong, Kin Leong Pey | 2002-04-02 |
| 6355563 | Versatile copper-wiring layout design with low-k dielectric integration | Randall Cher Liang Cha, Yeow Kheng Lim, Tae Jong Lee, Lap Chan | 2002-03-12 |
| 6348385 | Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant | Randall Cher Liang Cha, Tae Jong Lee, Lap Chan, Chee Tee Chua | 2002-02-19 |
| 6335253 | Method to form MOS transistors with shallow junctions using laser annealing | Yung Fu Chong, Kin Leong Pey, Andrew Thye Shen Wee | 2002-01-01 |