Issued Patents 2002
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6492249 | High-K gate dielectric process with process with self aligned damascene contact to damascene gate and a low-k inter level dielectric | Matthew S. Buynoski, Ming-Ren Lin | 2002-12-10 |
| 6486038 | Method for and device having STI using partial etch trench bottom liner | Witold P. Maszara, Ming-Ren Lin | 2002-11-26 |
| 6479866 | SOI device with self-aligned selective damage implant, and method | — | 2002-11-12 |
| 6475874 | Damascene NiSi metal gate high-k transistor | Paul R. Besser, Matthew S. Buynoski, John Foster, Paul L. King, Eric N. Paton | 2002-11-05 |
| 6465267 | Method of measuring gate capacitance to determine the electrical thickness of gate dielectrics | Haihong Wang | 2002-10-15 |
| 6465334 | Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors | Matthew S. Buynoski, Paul R. Besser, Paul L. King, Eric N. Paton | 2002-10-15 |
| 6465309 | Silicide gate transistors | Paul R. Besser, Matthew S. Buynoski, John Foster, Paul L. King, Eric N. Paton | 2002-10-15 |
| 6458679 | Method of making silicide stop layer in a damascene semiconductor structure | Eric N. Paton, Paul R. Besser, Matthew S. Buynoski, Paul L. King, John Foster | 2002-10-01 |
| 6451693 | Double silicide formation in polysicon gate without silicide in source/drain extensions | Christy Mei-Chu Woo, George Jonathan Kluth | 2002-09-17 |
| 6448127 | Process for formation of ultra-thin base oxide in high k/oxide stack gate dielectrics of mosfets | Joong S. Jeon, Colman Wong | 2002-09-10 |
| 6440806 | Method for producing metal-semiconductor compound regions on semiconductor devices | — | 2002-08-27 |
| 6440867 | Metal gate with PVD amorphous silicon and silicide for CMOS devices and method of making the same with a replacement gate process | Paul R. Besser, Matthew S. Buynoski | 2002-08-27 |
| 6440868 | Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process | Paul R. Besser, Matthew S. Buynoski | 2002-08-27 |
| 6441434 | Semiconductor-on-insulator body-source contact and method | Wei Long, Yowjuang W. Liu | 2002-08-27 |
| 6437404 | Semiconductor-on-insulator transistor with recessed source and drain | Wei Long, Ming-Ren Lin | 2002-08-20 |
| 6436840 | Metal gate with CVD amorphous silicon layer and a barrier layer for CMOS devices and method of making with a replacement gate process | Paul R. Besser, Matthew S. Buynoski | 2002-08-20 |
| 6433379 | Tantalum anodization for in-laid copper metallization capacitor | Sergey Lopatin, Steven C. Avanzino, Matthew S. Buynoski | 2002-08-13 |
| 6420770 | STI (Shallow Trench Isolation) structures for minimizing leakage current through drain and source silicides | Wei Long, Ming-Ren Lin | 2002-07-16 |
| 6417556 | High K dielectric de-coupling capacitor embedded in backend interconnect | Wei Long | 2002-07-09 |
| 6410938 | Semiconductor-on-insulator device with nitrided buried oxide and method of fabricating | — | 2002-06-25 |
| 6392280 | Metal gate with PVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process | Paul R. Besser, Matthew S. Buynoski | 2002-05-21 |
| 6376343 | Reduction of metal silicide/silicon interface roughness by dopant implantation processing | Matthew S. Buynoski, Paul R. Besser | 2002-04-23 |
| 6373103 | Semiconductor-on-insulator body-source contact using additional drain-side spacer, and method | Wei Long, Yowjuang W. Liu | 2002-04-16 |
| 6369429 | Low resistance composite contact structure utilizing a reaction barrier layer under a metal layer | Shekhar Pramanick, Ming-Ren Lin | 2002-04-09 |
| 6369421 | EEPROM having stacked dielectric to increase programming speed | Xiao-Yu Li | 2002-04-09 |