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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Dah-Bin Kao — 11 Patents

UNUnknown: 4 patents #4,220 of 83,584Top 6%
NSNational Semiconductor: 3 patents #635 of 2,238Top 30%
UMUnited Microelectronics: 3 patents #1,523 of 4,560Top 35%
GEGenus: 2 patents #14 of 76Top 20%
WAWinbond Electronics Corporation America: 1 patents #3 of 9Top 35%
WEWinbound Electronics: 1 patents #2 of 25Top 8%
WEWindbond Electronics: 1 patents #19 of 136Top 15%
Palo Alto, CA: #2,109 of 9,675 inventorsTop 25%
California: #56,011 of 386,348 inventorsTop 15%
Overall (All Time): #435,149 of 4,157,543Top 15%
11 Patents All Time
Dah-Bin Kao has been granted 11 US patents while listed as an inventor at Unknown. The first was granted in 1994 and the most recent in April 2005. Dah-Bin Kao ranks #435,149 of 4,157,543 US inventors in our database (top 10.5%). Patent records list Dah-Bin Kao in Palo Alto, CA, US.

Patents per Year

Patents granted per year, 1994 to 2005Bar chart with a peak of 3 patents in 2001.peak 31994: 1 patents19941996: 1 patents19961997: 1 patents19971998: 2 patents19981999: 2 patents19992001: 3 patents20012005: 1 patents2005

Issued Patents All Time

Showing 1–11 of 11 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
6876031 Method and apparatus for split gate source side injection flash memory cell and array with dedicated erase gates Loc B. Hoang, Albert Wu, Tung-Yi Chan 2005-04-05 $2,113,000
6323089 Semiconductor memory array with buried drain lines and processing methods therefor Loc B. Hoang, Albert Wu, Tung-Yi Chan 2001-11-27
6274436 Method for forming minute openings in semiconductor devices Albert Wu, Tung-Yi Chan 2001-08-14
6211547 Semiconductor memory array with buried drain lines and processing methods therefor Loc B. Hoang, Albert Wu, Tung-Yi Chan 2001-04-03
5986934 Semiconductor memory array with buried drain lines and methods therefor Loc B. Hoang, Albert Wu, Tung-Yi Chan 1999-11-16
5903487 Memory device and method of operation Albert Wu, Loc B. Hoang, Tung-Yi Chan 1999-05-11
5762755 Organic preclean for improving vapor phase wafer etch uniformity Michael A. McNeilly, John deLarios, Glenn Nobinger, Wilbur C. Krusell, Ralph K. Manriquez +1 more 1998-06-09 $346,000
5759882 Method of fabricating self-aligned contacts and local interconnects in CMOS and BICMOS processes using chemical mechanical polishing (CMP) John M. Pierce 1998-06-02 $7,648,000
5683941 Self-aligned polycide process that utilizes a planarized layer of material to expose polysilicon structures to a subsequently deposited metal layer that is reacted to form the metal silicide John M. Pierce 1997-11-04 $12,385,000
5492847 Counter-implantation method of manufacturing a semiconductor device with self-aligned anti-punchthrough pockets Gregory S. Scott 1996-02-20 $5,797,000
5294568 Method of selective etching native oxide Michael A. McNeilly, Bruce E. Deal, John M. de Larios 1994-03-15 $1,237,000