Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6876031 | Method and apparatus for split gate source side injection flash memory cell and array with dedicated erase gates | Loc B. Hoang, Albert Wu, Tung-Yi Chan | 2005-04-05 |
| 6323089 | Semiconductor memory array with buried drain lines and processing methods therefor | Loc B. Hoang, Albert Wu, Tung-Yi Chan | 2001-11-27 |
| 6274436 | Method for forming minute openings in semiconductor devices | Albert Wu, Tung-Yi Chan | 2001-08-14 |
| 6211547 | Semiconductor memory array with buried drain lines and processing methods therefor | Loc B. Hoang, Albert Wu, Tung-Yi Chan | 2001-04-03 |
| 5986934 | Semiconductor memory array with buried drain lines and methods therefor | Loc B. Hoang, Albert Wu, Tung-Yi Chan | 1999-11-16 |
| 5903487 | Memory device and method of operation | Albert Wu, Loc B. Hoang, Tung-Yi Chan | 1999-05-11 |
| 5762755 | Organic preclean for improving vapor phase wafer etch uniformity | Michael A. McNeilly, John deLarios, Glenn Nobinger, Wilbur C. Krusell, Ralph K. Manriquez +1 more | 1998-06-09 |
| 5759882 | Method of fabricating self-aligned contacts and local interconnects in CMOS and BICMOS processes using chemical mechanical polishing (CMP) | John M. Pierce | 1998-06-02 |
| 5683941 | Self-aligned polycide process that utilizes a planarized layer of material to expose polysilicon structures to a subsequently deposited metal layer that is reacted to form the metal silicide | John M. Pierce | 1997-11-04 |
| 5492847 | Counter-implantation method of manufacturing a semiconductor device with self-aligned anti-punchthrough pockets | Gregory S. Scott | 1996-02-20 |
| 5294568 | Method of selective etching native oxide | Michael A. McNeilly, Bruce E. Deal, John M. de Larios | 1994-03-15 |