JP

John M. Pierce

NS National Semiconductor: 9 patents #195 of 2,238Top 9%
FI Fairchild Camera & Instrument: 7 patents #6 of 173Top 4%
DE Develco: 1 patents #6 of 14Top 45%
LE Lear: 1 patents #905 of 1,996Top 50%
Overall (All Time): #225,982 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
6948645 Adjustable frame for retaining hand truck on vehicular body Bill Snowa, Billie M. Bloodworth 2005-09-27
6786373 Adjustable frame for retaining hand truck on vehicular body Bill Snowa 2004-09-07
6406093 Attachment for seat assembly Ronald L. Miotto, Kenneth R. Parrish, David R. Fabry, Benedict J. Messina, Cathy A. Sadler 2002-06-18
6008107 Method of planarizing integrated circuits with fully recessed isolation dielectric Sung Tae Ahn 1999-12-28
5883010 Method for protecting nonsilicided surfaces from silicide formation using spacer oxide mask Richard B. Merrill, C. S. Teng 1999-03-16
5759882 Method of fabricating self-aligned contacts and local interconnects in CMOS and BICMOS processes using chemical mechanical polishing (CMP) Dah-Bin Kao 1998-06-02
5683941 Self-aligned polycide process that utilizes a planarized layer of material to expose polysilicon structures to a subsequently deposited metal layer that is reacted to form the metal silicide Dah-Bin Kao 1997-11-04
5589412 Method of making increased-density flash EPROM that utilizes a series of planarized, self-aligned, intermediate strips of conductive material to contact the drain regions Ali A. Iranmanesh, Albert Bergemont 1996-12-31
5422289 Method of manufacturing a fully planarized MOSFET and resulting structure — 1995-06-06
5302551 Method for planarizing the surface of an integrated circuit over a metal interconnect layer Ali A. Iranmanesh 1994-04-12
5287663 Polishing pad and method for polishing semiconductor wafers Peter Renteln 1994-02-22
5094972 Means of planarizing integrated circuits with fully recessed isolation dielectric Sung Tae Ahn 1992-03-10
4727048 Process for making isolated semiconductor structure William I. Lehrer 1988-02-23
4630343 Product for making isolated semiconductor structure William I. Lehrer 1986-12-23
4619844 Method and apparatus for low pressure chemical vapor deposition William I. Lehrer 1986-10-28
4489482 Impregnation of aluminum interconnects with copper Thomas Keyser, Michael E. Thomas, James M. Cleeves 1984-12-25
4490737 Smooth glass insulating film over interconnects on an integrated circuit William I. Lehrer 1984-12-25
4352239 Process for suppressing electromigration in conducting lines formed on integrated circuits by control of crystalline boundary orientation — 1982-10-05
4267012 Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer William I. Lehrer, Kenneth Radigan 1981-05-12
4221834 Superconductive magnetic shield and method of making same James E. Opfer, Lawrence E. Valby 1980-09-09