Issued Patents All Time
Showing 26–49 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7038935 | 2-terminal trapped charge memory device with voltage switchable multi-level resistance | Darrell Rinerson, Wayne Kinney, Steven W. Longcor, Edmond R. Ward, Christophe J. Chevallier | 2006-05-02 |
| 6972985 | Memory element having islands | Darrell Rinerson, Christophe J. Chevallier, Philip Swab, John Sanchez, Steven W. Longcor | 2005-12-06 |
| 6970375 | Providing a reference voltage to a cross point memory array | Darrell Rinerson, Christophe J. Chevallier, Steven W. Longcor, Edmond R. Ward, Wayne Kinney | 2005-11-29 |
| 6965137 | Multi-layer conductive memory device | Wayne Kinney, Steven W. Longcor, Darrell Rinerson | 2005-11-15 |
| 6917539 | High-density NVRAM | Darrell Rinerson, Steven W. Longcor, Edmond R. Ward, Wayne Kinney | 2005-07-12 |
| 6909632 | Multiple modes of operation in a cross point array | Darrell Rinerson, Christophe J. Chevallier, Steven W. Longcor, Edmond R. Ward, Wayne Kinney | 2005-06-21 |
| 6873004 | Virtual ground single transistor memory cell, memory array incorporating same, and method of operation thereof | Kyung Joon Han, Joo Weon Park, Gyu Wan Kwon, Jong Seuk Lee | 2005-03-29 |
| 6870755 | Re-writable memory with non-linear memory element | Darrell Rinerson, Christophe J. Chevallier, Steven W. Longcor, Wayne Kinney, Edmond R. Ward | 2005-03-22 |
| 6850429 | Cross point memory array with memory plugs exhibiting a characteristic hysteresis | Darrell Rinerson, Steven W. Longcor, Wayne Kinney, Edmond R. Ward, Christophe J. Chevallier | 2005-02-01 |
| 6834008 | Cross point memory array using multiple modes of operation | Darrell Rinerson, Christophe J. Chevallier, Steven W. Longcor, Edmond R. Ward, Wayne Kinney | 2004-12-21 |
| 6831854 | Cross point memory array using distinct voltages | Darrell Rinerson, Steven W. Longcor, Christophe J. Chevallier, Edmond R. Ward, Wayne Kinney | 2004-12-14 |
| 6798685 | Multi-output multiplexor | Darrell Rinerson, Christophe J. Chevallier, Steven W. Longcor | 2004-09-28 |
| 6753561 | Cross point memory array using multiple thin films | Darrell Rinerson, Steven W. Longcor, Edmond R. Ward, Wayne Kinney, Christophe J. Chevallier | 2004-06-22 |
| 6747899 | Method and apparatus for multiple byte or page mode programming of a flash memory array | Kyung Joon Han, Dung Q. Tran | 2004-06-08 |
| 6731544 | Method and apparatus for multiple byte or page mode programming of a flash memory array | Kyung Joon Han, Dung Q. Tran, Steven W. Longcor | 2004-05-04 |
| 6728140 | Threshold voltage convergence | Kyung Joon Han, Joo Weon Park, Gyu Wan Kwon, Dung Q. Tran, Jong Seuk Lee +1 more | 2004-04-27 |
| 6562724 | Self-aligned stack formation | Yin Hu | 2003-05-13 |
| 5969397 | Low defect density composite dielectric | Douglas Ticknor Grider, Paul Edward Nicollian | 1999-10-19 |
| 5313429 | Memory circuit with pumped voltage for erase and program operations | Christophe J. Chevallier, Asim A. Bajwa, Darrell Rinerson | 1994-05-17 |
| 5185718 | Memory array architecture for flash memory | Darrell Rinerson, Christophe J. Chevallier, Chan-Sui Pang | 1993-02-09 |
| 5033023 | High density EEPROM cell and process for making the cell | Chan-Sui Pang, Christopher J. Chevallier | 1991-07-16 |
| 4894802 | Nonvolatile memory cell for eeprom including a floating gate to drain tunnel area positioned away from the channel region to prevent trapping of electrons in the gate oxide during cell erase | Chan-Sui Pang | 1990-01-16 |
| 4861730 | Process for making a high density split gate nonvolatile memory cell | Pritpal S. Mahal, Wei-Ren Shih | 1989-08-29 |
| 4577391 | Method of manufacturing CMOS devices | Paul Chang | 1986-03-25 |