Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7606074 | Word line compensation in non-volatile memory erase operations | Jun Wan, Jeffrey W. Lutze | 2009-10-20 |
| 7450433 | Word line compensation in non-volatile memory erase operations | Jun Wan, Jeffrey W. Lutze | 2008-11-11 |
| 7057931 | Flash memory programming using gate induced junction leakage current | Jeffrey W. Lutze | 2006-06-06 |
| 6798012 | Dual-bit double-polysilicon source-side injection flash EEPROM cell | Yueh Yale Ma | 2004-09-28 |
| 6714454 | Method of operation of a dual-bit double-polysilicon source-side injection flash EEPROM cell | Yueh Yale Ma | 2004-03-30 |
| 6493262 | Method for operating nonvolatile memory cells | Keith R. Wald, Yueh Yale Ma | 2002-12-10 |
| 5986941 | Programming current limiter for source-side injection EEPROM cells | Yueh Yale Ma | 1999-11-16 |
| 5663907 | Switch driver circuit for providing small sector sizes for negative gate erase flash EEPROMS using a standard twin-well CMOS process | Jack Edward Frayer, John Lattanzi, Shouchang Tsao, Yueh Yale Ma | 1997-09-02 |
| D336316 | Toy motorcycle | Cheung W. Keung | 1993-06-08 |
| 5185718 | Memory array architecture for flash memory | Darrell Rinerson, Steve Kuo-Ren Hsia, Christophe J. Chevallier | 1993-02-09 |
| 5033023 | High density EEPROM cell and process for making the cell | Steve Kuo-Ren Hsia, Christopher J. Chevallier | 1991-07-16 |
| 4894802 | Nonvolatile memory cell for eeprom including a floating gate to drain tunnel area positioned away from the channel region to prevent trapping of electrons in the gate oxide during cell erase | Steve Kuo-Ren Hsia | 1990-01-16 |
| 4807003 | High-reliablity single-poly eeprom cell | Farrokh Mohammadi | 1989-02-21 |