Issued Patents All Time
Showing 51–75 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5838044 | Integrated circuit having improved polysilicon resistor structures | Yowjuang W. Liu | 1998-11-17 |
| 5831894 | Methods of programming and reading one time programmable read only memory | — | 1998-11-03 |
| 5821146 | Method of fabricating FET or CMOS transistors using MeV implantation | Yowjuang W. Liu, Mark I. Gardner, Fred N. Hause | 1998-10-13 |
| 5811347 | Nitrogenated trench liner for improved shallow trench isolation | Mark I. Gardner, Fred N. Hause | 1998-09-22 |
| 5786247 | Low voltage CMOS process with individually adjustable LDD spacers | Ramachandr A. Rao | 1998-07-28 |
| 5763937 | Device reliability of MOS devices using silicon rich plasma oxide films | Vivek Jain, Dipankar Pramanik, Subhash R. Nariani | 1998-06-09 |
| 5750428 | Self-aligned non-volatile process with differentially grown gate oxide thickness | — | 1998-05-12 |
| 5737259 | Method of decoding a diode type read only memory | — | 1998-04-07 |
| 5734179 | SRAM cell having single layer polysilicon thin film transistors | Yowjuang W. Liu | 1998-03-31 |
| 5712195 | Method for making via structure with metallic spacer | — | 1998-01-27 |
| 5693568 | Reverse damascene via structures | Yowjuang W. Liu | 1997-12-02 |
| 5643825 | Integrated circuit isolation process | Mark I. Gardner, Fred N. Hause | 1997-07-01 |
| 5610088 | Method of fabricating field effect transistors having lightly doped drain regions | Yowjuang W. Liu | 1997-03-11 |
| 5608253 | Advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits | Yowjuang W. Liu | 1997-03-04 |
| 5602056 | Method for forming reliable MOS devices using silicon rich plasma oxide film | Vivek Jain, Dipankar Pramanik, Subhash R. Nariani | 1997-02-11 |
| 5587332 | Method of making flash memory cell | Subhash R. Nariani, William J. Boardman | 1996-12-24 |
| 5565703 | Multi-level antifuse structure | — | 1996-10-15 |
| 5554562 | Advanced isolation scheme for deep submicron technology | Yowjuang W. Liu, Mark I. Gardner, Frederick N. Hause | 1996-09-10 |
| 5512506 | Lightly doped drain profile optimization with high energy implants | Mark I. Gardner, Frederick N. Hause | 1996-04-30 |
| 5504364 | CMOS locos isolation for self-aligned NPN BJT in a BiCMOS process | Yi Wei | 1996-04-02 |
| 5493152 | Conductive via structure for integrated circuits and method for making same | — | 1996-02-20 |
| 5492865 | Method of making structure for suppression of field inversion caused by charge build-up in the dielectric | Subhash R. Nariani, Vivek Jain, Dipankar Pramanik | 1996-02-20 |
| 5493132 | Integrated circuit contact barrier formation with ion implant | Hunter B. Brugge, Felix Fujishiro, Chang-Ou Lee, Walter D. Parmantie | 1996-02-20 |
| 5489540 | Method of making simplified LDD and source/drain formation in advanced CMOS integrated circuits using implantation through well mask | Yowjuang W. Liu | 1996-02-06 |
| 5434098 | Double poly process with independently adjustable interpoly dielectric thickness | — | 1995-07-18 |