Issued Patents All Time
Showing 76–87 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5427979 | Method for making multi-level antifuse structure | — | 1995-06-27 |
| 5374833 | Structure for suppression of field inversion caused by charge build-up in the dielectric | Subhash R. Nariani, Vivek Jain, Dipankar Pramanik | 1994-12-20 |
| 5371393 | EEPROM cell with improved tunneling properties | Subhash R. Nariani | 1994-12-06 |
| 5328865 | Method for making cusp-free anti-fuse structures | William J. Boardman, David P. Chan, Calvin T. Gabriel, Vivek Jain, Subhash R. Nariani | 1994-07-12 |
| 5290734 | Method for making anti-fuse structures | William J. Boardman, David P. Chan, Calvin T. Gabriel, Vivek Jain, Subhash R. Nariani | 1994-03-01 |
| 5198381 | Method of making an E.sup.2 PROM cell with improved tunneling properties having two implant stages | Subhash R. Nariani | 1993-03-30 |
| 5120679 | Anti-fuse structures and methods for making same | William J. Boardman, David P. Chan, Calvin T. Gabriel, Vivek Jain, Subhash R. Nariani | 1992-06-09 |
| 4987465 | Electro-static discharge protection device for CMOS integrated circuit inputs | Steven W. Longcor, Jih-Chang Lien, David Michael Rogers | 1991-01-22 |
| 4775642 | Modified source/drain implants in a double-poly non-volatile memory process | Charles Frederick Hart, Yee-Chaung See | 1988-10-04 |
| 4764477 | CMOS process flow with small gate geometry LDO N-channel transistors | Charles Frederick Hart | 1988-08-16 |
| 4683488 | Latch-up resistant CMOS structure for VLSI including retrograded wells | William W. Lee | 1987-07-28 |
| 4645562 | Double layer photoresist technique for side-wall profile control in plasma etching processes | Kuan-Yang Liao, Hsing-Chien Ma | 1987-02-24 |