Issued Patents All Time
Showing 1–25 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12137156 | Physical layer to link layer interface and related systems, methods and devices | Dixon Chen, John Junling Zang, Shivanand I. Akkihal | 2024-11-05 |
| 12019573 | Continuous adaptive data capture optimization for interface circuits | Jung Lee, Brett Murdock | 2024-06-25 |
| 12014767 | Double data rate (DDR) memory controller apparatus and method | Mahesh Gopalan, David Wu | 2024-06-18 |
| 11876616 | Changing a master node in a wired local area network and related systems, methods, and devices | Michael Rentschler, Martin Miller, Thorben Link | 2024-01-16 |
| 11723151 | Methods of creating exposed cavities in molded electronic devices | Dongkai Shangguan, David Geiger, Cheng Yang | 2023-08-08 |
| 11714769 | Continuous adaptive data capture optimization for interface circuits | Jung Lee, Brett Murdock | 2023-08-01 |
| 11710516 | Double data rate (DDR) memory controller apparatus and method | Mahesh Gopalan, David Wu | 2023-07-25 |
| 11348632 | Double data rate (DDR) memory controller apparatus and method | Mahesh Gopalan, David Wu | 2022-05-31 |
| 11334509 | Continuous adaptive data capture optimization for interface circuits | Jung Lee, Brett Murdock | 2022-05-17 |
| 11304302 | Methods of creating exposed cavities in molded electronic devices | Dongkai Shangguan, David Geiger, Cheng Yang | 2022-04-12 |
| 11171732 | Ethernet interface and related systems methods and devices | Dixon Chen, John Junling Zang, Shivanand I. Akkihal | 2021-11-09 |
| 10896877 | System in package with double side mounted board | Cheng Yang, Dongkai Shangguan, Bo Li | 2021-01-19 |
| 10734061 | Double data rate (DDR) memory controller apparatus and method | Mahesh Gopalan, David Wu | 2020-08-04 |
| 10586585 | Double data rate (DDR) memory controller apparatus and method | Mahesh Gopalan, David Wu | 2020-03-10 |
| 10269408 | Double data rate (DDR) memory controller apparatus and method | Mahesh Gopalan, David Wu | 2019-04-23 |
| 10242730 | Double data rate (DDR) memory controller apparatus and method | Mahesh Gopalan, David Wu | 2019-03-26 |
| 10229729 | Method for calibrating capturing read data in a read data path for a DDR memory interface circuit | Mahesh Gopalan, David Wu | 2019-03-12 |
| 10032502 | Method for calibrating capturing read data in a read data path for a DDR memory interface circuit | Mahesh Gopalan, David Wu | 2018-07-24 |
| 9898433 | Continuous adaptive data capture optimization for interface circuits | Jung Lee, Brett Murdock | 2018-02-20 |
| 9805784 | Multiple gating modes and half-frequency dynamic calibration for DDR memory controllers | Mahesh Gopalan, David Wu | 2017-10-31 |
| 9431091 | Multiple gating modes and half-frequency dynamic calibration for DDR memory controllers | Mahesh Gopalan, David Wu | 2016-08-30 |
| 9425778 | Continuous adaptive data capture optimization for interface circuits | Jung Lee, Brett Murdock | 2016-08-23 |
| 9291472 | Audible consumption of content while traveling to a destination | Venkitesh Subramanian, Prerna Makanawala, Lin Pang, Ryan Currier | 2016-03-22 |
| 9159656 | Semiconductor die package and method for making the same | Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina Estacio, David Chong +6 more | 2015-10-13 |
| 9100027 | Data interface circuit for capturing received data bits including continuous calibration | Prashant Joshi, Jung Lee | 2015-08-04 |