Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12105161 | Layouts for interlevel crack prevention in fluxgate technology manufacturing | Sudtida Lavangkul | 2024-10-01 |
| 11508721 | Integrated fluxgate device | Mona Eissa, Mark R. Kimmich, Sudtida Lavangkul, Mark L. Jenson | 2022-11-22 |
| 11121207 | Integrated trench capacitor with top plate having reduced voids | Binghua Hu, Abbas Ali, Jarvis Benjamin Jacobs | 2021-09-14 |
| 10978448 | Integrated fluxgate device | Mona Eissa, Mark R. Kimmich, Sudtida Lavangkul, Mark L. Jenson | 2021-04-13 |
| 10005662 | Selective patterning of titanium encapsulation layers | Lee Alan Stringer, Mona Eissa, Byron J.R. Shulver, Mark R. Kimmich, Sudtida Lavangkul +1 more | 2018-06-26 |
| 9771261 | Selective patterning of an integrated fluxgate device | Lee Alan Stringer, Mona Eissa, Byron J.R. Shulver, Mark R. Kimmich, Sudtida Lavangkul +1 more | 2017-09-26 |
| 9691751 | In-situ doped polysilicon filler for trenches | Bhaskar Srinivasan, Khanh Quang Le, Collin White, Ashley J. Norris, Bernard John Fischer | 2017-06-27 |
| 8334190 | Single step CMP for polishing three or more layer film stacks | Eugene C. Davis, Binghua Hu, Prakash Dalpatbhai Dev | 2012-12-18 |
| 8110414 | Forming integrated circuit devices with metal-insulator-metal capacitors using selective etch of top electrodes | Marshall O. Cathey, Jr., Pushpa Mahalingam, Weidong Tian, David C. Guiling, Xinfen Chen +1 more | 2012-02-07 |
| 7745335 | Semiconductor device manufactured by reducing hillock formation in metal interconnects | Ju-Ai Ruan, Changming Jin, Satyavolu Papa Rao, Tae Seung Kim | 2010-06-29 |
| 7727885 | Reduction of punch-thru defects in damascene processing | Phillip D. Matz, Ching-Te Lin, Basab Chatterjee, Anand J. Reddy, Kenneth Newton +1 more | 2010-06-01 |