MS

Margaret Simmons-Matthews

TI Texas Instruments: 14 patents #973 of 12,488Top 8%
📍 Richardson, TX: #186 of 2,156 inventorsTop 9%
🗺 Texas: #10,587 of 125,132 inventorsTop 9%
Overall (All Time): #352,518 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Showing 1–14 of 14 patents

Patent #TitleCo-InventorsDate
8815642 Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies Jeffrey Alan West, Raymundo M. Camenforte 2014-08-26
8759154 TCE compensation for package substrates for reduced die warpage assembly 2014-06-24
8597978 Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint Kurt Peter Wachtler 2013-12-03
8575758 Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies Jeffrey Alan West, Raymundo M. Camenforte 2013-11-05
8526186 Electronic assembly including die on substrate with heat spreader having an open window on the die Satoshi Yokoya 2013-09-03
8471577 Lateral coupling enabled topside only dual-side testing of TSV die attached to package substrate Daniel Stillman, James L. Oborny, William John Antheunisse, Norman J. Armendariz, Ramyanshu Datta +1 more 2013-06-25
8344749 Through carrier dual side loop-back testing of TSV die after die attach to substrate Daniel Stillman, James L. Oborny, William John Antheunisse, Norman J. Armendariz, Ramyanshu Datta +1 more 2013-01-01
8344493 Warpage control features on the bottomside of TSV die lateral to protruding bottomside tips Jeffrey Alan West, Jeffrey E. Brighton 2013-01-01
8313982 Stacked die assemblies including TSV die Rajiv Dunne 2012-11-20
8298863 TCE compensation for package substrates for reduced die warpage assembly 2012-10-30
8288849 Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint Kurt Peter Wachtler 2012-10-16
8227295 IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV Donald C. Abbott 2012-07-24
8097964 IC having TSV arrays with reduced TSV induced stress Jeffrey Alan West, Masazumi Amagai 2012-01-17
6768212 Semiconductor packages and methods for manufacturing such semiconductor packages Akira Karashima, Sohichi Kadoguchi 2004-07-27