Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9412869 | MOSFET with source side only stress | Samuel Zafar Nawaz, Shaofeng Yu, Song Zhao | 2016-08-09 |
| 8928047 | MOSFET with source side only stress | Samuel Zafar Nawaz, Shaofeng Yu, Song Zhao | 2015-01-06 |
| 8344493 | Warpage control features on the bottomside of TSV die lateral to protruding bottomside tips | Jeffrey Alan West, Margaret Simmons-Matthews | 2013-01-01 |
| 6713361 | Method of manufacturing a bipolar junction transistor including undercutting regions adjacent to the emitter region to enlarge the emitter region | Samuel Zafar Nawaz | 2004-03-30 |
| 5436199 | Pillar alignment and formation process | — | 1995-07-25 |
| 5212352 | Self-aligned tungsten-filled via | Douglas P. Verret | 1993-05-18 |
| 5132775 | Methods for and products having self-aligned conductive pillars on interconnects | Bobby A. Roane | 1992-07-21 |
| 5104816 | Polysilicon self-aligned bipolar device including trench isolation and process of manufacturing same | Douglas P. Verret, Deems R. Hollingsworth, Manuel L. Torreno, Jr. | 1992-04-14 |
| 5025303 | Product of pillar alignment and formation process | — | 1991-06-18 |
| 4996133 | Self-aligned tungsten-filled via process and via formed thereby | Douglas P. Verret | 1991-02-26 |
| 4979010 | VLSI self-aligned bipolar transistor | — | 1990-12-18 |
| 4966865 | Method for planarization of a semiconductor device prior to metallization | Michael T. Welch, Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr. | 1990-10-30 |
| 4931144 | Self-aligned nonnested sloped via | — | 1990-06-05 |
| 4866008 | Methods for forming self-aligned conductive pillars on interconnects | Bobby A. Roane | 1989-09-12 |
| 4842991 | Self-aligned nonnested sloped via | — | 1989-06-27 |
| 4839305 | Method of making single polysilicon self-aligned transistor | — | 1989-06-13 |
| 4799099 | Bipolar transistor in isolation well with angled corners | Douglas P. Verret, Deems R. Hollingsworth, Manuel L. Torreno, Jr. | 1989-01-17 |
| 4795722 | Method for planarization of a semiconductor device prior to metallization | Michael T. Welch, Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr. | 1989-01-03 |
| 4789885 | Self-aligned silicide in a polysilicon self-aligned bipolar transistor | Deems R. Hollingsworth, Michael T. Welch, Ronald E. McMann, Manuel L. Torreno, Jr., Charles Wayne Sullivan | 1988-12-06 |
| 4753709 | Method for etching contact vias in a semiconductor device | Michael T. Welch, Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr. | 1988-06-28 |