Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5017510 | Method of making a scalable fuse link element | Michael T. Welch, Manuel L. Torreno, Jr., Evaristo Garcia, Jr. | 1991-05-21 |
| 4966865 | Method for planarization of a semiconductor device prior to metallization | Michael T. Welch, Manuel L. Torreno, Jr., Evaristo Garcia, Jr., Jeffrey E. Brighton | 1990-10-30 |
| 4954423 | Planar metal interconnection for a VLSI device | Evaristo Garcia, Jr., Michael T. Welch, Stephen W. Thompson | 1990-09-04 |
| 4862243 | Scalable fuse link element | Michael T. Welch, Manuel L. Torreno, Jr., Evaristo Garcia, Jr. | 1989-08-29 |
| 4795722 | Method for planarization of a semiconductor device prior to metallization | Michael T. Welch, Manuel L. Torreno, Jr., Evaristo Garcia, Jr., Jeffrey E. Brighton | 1989-01-03 |
| 4789885 | Self-aligned silicide in a polysilicon self-aligned bipolar transistor | Jeffrey E. Brighton, Deems R. Hollingsworth, Michael T. Welch, Manuel L. Torreno, Jr., Charles Wayne Sullivan | 1988-12-06 |
| 4753709 | Method for etching contact vias in a semiconductor device | Michael T. Welch, Manuel L. Torreno, Jr., Evaristo Garcia, Jr., Jeffrey E. Brighton | 1988-06-28 |