Issued Patents All Time
Showing 26–50 of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8435848 | PMOS SiGe-last integration process | — | 2013-05-07 |
| 7960238 | Multiple indium implant methods and devices and integrated circuits therefrom | Puneet Kohli | 2011-06-14 |
| 7897496 | Semiconductor doping with reduced gate edge diode leakage | Puneet Kohli, Nandakumar Mahalingam, Song Zhao | 2011-03-01 |
| 7846783 | Use of poly resistor implant to dope poly gates | Puneet Kohli | 2010-12-07 |
| 7736983 | High threshold NMOS source-drain formation with As, P and C to reduce damage | Puneet Kohli, Shaoping Tang | 2010-06-15 |
| 7691700 | Multi-stage implant to improve device characteristics | Stan Ashburn, Shaoping Tang | 2010-04-06 |
| 7670917 | Semiconductor device made by using a laser anneal to incorporate stress into a channel region | Amitabh Jain | 2010-03-02 |
| 7615458 | Activation of CMOS source/drain extensions by ultra-high temperature anneals | Amitabh Jain | 2009-11-10 |
| 7611939 | Semiconductor device manufactured using a laminated stress layer | Antonio L. P. Rotondaro, Puneet Kohli | 2009-11-03 |
| 7524777 | Method for manufacturing an isolation structure using an energy beam treatment | Puneet Kohli, Jin Zhao, Sameer Ajmera | 2009-04-28 |
| 7510923 | Slim spacer implementation to improve drive current | Karen Hildegard Ralston Kirmse, Shirin Siddiqui | 2009-03-31 |
| 7465635 | Method for manufacturing a gate sidewall spacer using an energy beam treatment | Puneet Kohli, Jin Zhao, Sameer Ajmera | 2008-12-16 |
| 7344929 | Method for manufacturing an integrated circuit using a capping layer having a degree of reflectivity | Amitabh Jain | 2008-03-18 |
| 7279397 | Shallow trench isolation method | Amitava Chatterjee | 2007-10-09 |
| 7211481 | Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer | Lahir Shaik Adam, Song Zhao, Mahalingam Nandakumar | 2007-05-01 |
| 7199020 | Nitridation of STI liner oxide for modulating inverse width effects in semiconductor devices | Hiroaki Niimi | 2007-04-03 |
| 6987061 | Dual salicide process for optimum performance | — | 2006-01-17 |
| 6743705 | Transistor with improved source/drain extension dopant concentration | Haowen Bu, Amitabh Jain | 2004-06-01 |
| 6737325 | Method and system for forming a transistor having source and drain extensions | Reima Laaksonen | 2004-05-18 |
| 6686300 | Sub-critical-dimension integrated circuit features | John N. Randall, Mark S. Rodder | 2004-02-03 |
| 6677208 | Transistor with bottomwall/sidewall junction capacitance reduction region and method | Kaiping Liu | 2004-01-13 |
| 6635584 | Versatile system for forming uniform wafer surfaces | Zhiqiang Wu, Mark S. Rodder | 2003-10-21 |
| 6599802 | Low-voltage-Vt (CMOS) transistor design using a single mask and without any additional implants by way of tailoring the effective channel length (Leff) | — | 2003-07-29 |
| 6482688 | Utilizing amorphorization of polycrystalline structures to achieve T-shaped MOSFET gate | Chimin Hu, Amitabh Jain, Reima Laaksonen | 2002-11-19 |
| 6352900 | Controlled oxide growth over polysilicon gates for improved transistor characteristics | Jerry Hu, Amitava Chatterjee, Mark S. Rodder | 2002-03-05 |