Issued Patents All Time
Showing 201–225 of 227 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5296393 | Process for the simultaneous fabrication of high-and-low-voltage semiconductor devices, integrated circuit containing the same, systems and methods | Louis N. Hutter, Georges Falessi, James Robert Todd, Manuel J. Torreno, Jr. deceased | 1994-03-22 |
| 5275961 | Method of forming insulated gate field-effect transistors | Jack Reynolds | 1994-01-04 |
| 5272098 | Vertical and lateral insulated-gate, field-effect transistors, systems and methods | James Robert Todd, Louis N. Hutter | 1993-12-21 |
| 5266517 | Method for forming a sealed interface on a semiconductor device | Jack Reynolds | 1993-11-30 |
| 5245543 | Method and apparatus for integrated circuit design | Georges Falessi | 1993-09-14 |
| 5242841 | Method of making LDMOS transistor with self-aligned source/backgate and photo-aligned gate | Manuel L. Torreno, Jr., George Falessi | 1993-09-07 |
| 5225700 | Circuit and method for forming a non-volatile memory cell | — | 1993-07-06 |
| 5204541 | Gated thyristor and process for its simultaneous fabrication with high- and low-voltage semiconductor devices | Lembit Soobik | 1993-04-20 |
| 5157281 | Level-shifter circuit for integrated circuits | Giovanni Santin, Sebastiano D'Arrigo | 1992-10-20 |
| 5145798 | Method of fabricating an insulated gate field effect transistor having lightly-doped source and drain extensions using an oxide sidewall spacer method | Michael Duane | 1992-09-08 |
| 5023690 | Merged bipolar and complementary metal oxide semiconductor transistor device | Douglas P. Verret, Abnash C. Sachdeva, Stephen A. Keller | 1991-06-11 |
| 4996668 | Erasable programmable memory | James L. Paterson | 1991-02-26 |
| 4939558 | EEPROM memory cell and driving circuitry | Sebastiano D'Arrigo | 1990-07-03 |
| 4912676 | Erasable programmable memory | James L. Paterson | 1990-03-27 |
| 4823320 | Electrically programmable fuse circuit for an integrated-circuit chip | Sebastiano D'Arrigo, Giuliano Imondi, Sossio Vergara | 1989-04-18 |
| 4804637 | EEPROM memory cell and driving circuitry | Sebastiano D'Arrigo | 1989-02-14 |
| 4797372 | Method of making a merge bipolar and complementary metal oxide semiconductor transistor device | Douglas P. Verret, Abnash C. Sachdeva, Stephen A. Keller | 1989-01-10 |
| 4742492 | EEPROM memory cell having improved breakdown characteristics and driving circuitry therefor | Sebastiano D'Arrigo | 1988-05-03 |
| 4736342 | Method of forming a field plate in a high voltage array | Giuliano Imondi, Sossio Vergara, Sebastiano D'Arrigo | 1988-04-05 |
| 4718041 | EEPROM memory having extended life | David A. Baglee | 1988-01-05 |
| 4715014 | Modified three transistor EEPROM cell | James A. Tuvell | 1987-12-22 |
| 4695979 | Modified four transistor EEPROM cell | James A. Tuvell | 1987-09-22 |
| 4669177 | Process for making a lateral bipolar transistor in a standard CSAG process | Sebastiano D'Arrigo | 1987-06-02 |
| 4628487 | Dual slope, feedback controlled, EEPROM programming | — | 1986-12-09 |
| 4569117 | Method of making integrated circuit with reduced narrow-width effect | David A. Baglee, Michael Duane, Mamoru Itoh | 1986-02-11 |