Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9406388 | Memory area protection system and methods | Luca De Santis, Maria-Luisa Gallese | 2016-08-02 |
| 8451661 | Programming methods and memories | Alessandro Torsi | 2013-05-28 |
| 8139419 | Programming methods and memories | Alessandro Torsi | 2012-03-20 |
| 7949844 | Pipelined burst memory access | Maurizio Di Zenzo, Mario Fazio | 2011-05-24 |
| 7565587 | Background block erase check for flash memories | Giovanni Naso | 2009-07-21 |
| 7363452 | Pipelined burst memory access | Maurizio Di Zenzo, Mario Fazio | 2008-04-22 |
| 7263022 | No-precharge FAMOS cell and latch circuit in a memory device | — | 2007-08-28 |
| 7164607 | Dual bus memory burst architecture | Girolamo Gallo, Giovanni Naso, Tommaso Vali | 2007-01-16 |
| 7154800 | No-precharge FAMOS cell and latch circuit in a memory device | — | 2006-12-26 |
| 7117402 | Background block erase check for flash memories | Maurizio Di Zenzo, Maria-Luisa Gallese, Giovanni Naso | 2006-10-03 |
| 7020737 | Pipelined burst memory access | Maurizio Di Zenzo, Mario Fazio | 2006-03-28 |
| 6967889 | No-precharge FAMOS cell and latch circuit in a memory device | — | 2005-11-22 |
| 6917545 | Dual bus memory burst architecture | Girolamo Gallo, Giovanni Naso, Tommaso Vali | 2005-07-12 |
| 6005820 | Field memories | Stefano Menichelli, Carlo Sansone | 1999-12-21 |
| 5457771 | Integrated circuit with non-volatile, variable resistor, for use in neuronic network | Giulio Marotta, Eros Pasero, Giulio Porrovecchio, Giuseppe Savarese | 1995-10-10 |
| 5319604 | Circuitry and method for selectively switching negative voltages in CMOS integrated circuits | Giulio Marotta, Giulio Porrovecchio, Giuseppe Savarese | 1994-06-07 |
| 5299286 | Data processing system for implementing architecture of neural network subject to learning process | Giulio Marotta, Giulio Porrovecchio, Giuseppe Savarese, Luciano Talamonti | 1994-03-29 |
| 5274743 | Learning system for a neural net of a suitable architecture, physically insertable in the learning process | Giulio Marotta, Giulio Porrovecchio, Giuseppe Savarese | 1993-12-28 |
| 5265052 | Wordline driver circuit for EEPROM memory cell | Sebastiano D'Arrigo, Sung-Wei Lin | 1993-11-23 |
| 4823320 | Electrically programmable fuse circuit for an integrated-circuit chip | Michael C. Smayling, Sebastiano D'Arrigo, Sossio Vergara | 1989-04-18 |
| 4823318 | Driving circuitry for EEPROM memory cell | Sebastiano D'Arrigo, Sung-Wei Lin, Manzur Gill | 1989-04-18 |
| 4760555 | Memory array with an array reorganizer | Tito Gelsomini | 1988-07-26 |
| 4736342 | Method of forming a field plate in a high voltage array | Michael C. Smayling, Sossio Vergara, Sebastiano D'Arrigo | 1988-04-05 |
| 4723114 | Method and circuit for trimming the frequency of an oscillator | Sebastiano D'Arrigo, Sossio Vergara | 1988-02-02 |
| 4716322 | Power-up control circuit including a comparator, Schmitt trigger, and latch | Sebastiano D'Arrigo, Sossio Vergara | 1987-12-29 |