Issued Patents All Time
Showing 176–200 of 227 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5589697 | Charge pump circuit with capacitors | Luciano Talamonti | 1996-12-31 |
| 5585657 | Windowed and segmented linear geometry source cell for power DMOS processes | Taylor R. Efland, Roy Clifton Jones, III, Oh-Kyong Kwon, Satwinder Malhi, Wai Tung Ng | 1996-12-17 |
| 5585294 | Method of fabricating lateral double diffused MOS (LDMOS) transistors | Manuel L. Torreno, Jr. | 1996-12-17 |
| 5567550 | Method of making a mask for making integrated circuits | — | 1996-10-22 |
| 5557569 | Low voltage flash EEPROM C-cell using fowler-nordheim tunneling | Giulio Marotta, Iano D'Arrigo, Giovanni Santin, Georges Falessi, Mousumi Bhat | 1996-09-17 |
| 5515319 | Non-volatile memory cell and level shifter | Iano D'Arrigo, Giovanni Santin, Georges Falessi, Mousumi Bhat | 1996-05-07 |
| 5504706 | Low voltage Fowler-Nordheim flash EEPROM memory array utilizing single level poly cells | Iano D'Arrigo, Georges Falessi | 1996-04-02 |
| 5504708 | Flash EEPROM array with P-tank insulated from substrate by deep N-tank | Giovanni Santin, Giovanni Naso, Sebastiano D'Arrigo | 1996-04-02 |
| 5504451 | Gated thyristor and process for its simultaneous fabrication with high- and low-voltage semiconductor devices, integrated circuit containing the same, systems and methods. | Lembit Soobik | 1996-04-02 |
| 5500548 | Non-epitaxial CMOS structures and processors | — | 1996-03-19 |
| 5500392 | Planar process using common alignment marks for well implants | James Reynolds | 1996-03-19 |
| 5491105 | LDMOS transistor with self-aligned source/backgate and photo-aligned gate | Manuel L. Torreno, Jr., Georges Falessi | 1996-02-13 |
| 5479040 | Charge pump circuit with field oxide regions | Luciano Talamonti | 1995-12-26 |
| 5467307 | Memory array utilizing low voltage Fowler-Nordheim Flash EEPROM cell | Iano D'Arrigo, Georges Falessi | 1995-11-14 |
| 5432740 | Low voltage flash EEPROM memory cell with merge select transistor and non-stacked gate structure | Iano D'Arrigo, Georges Falessi | 1995-07-11 |
| 5429959 | Process for simultaneously fabricating a bipolar transistor and a field-effect transistor | — | 1995-07-04 |
| 5420522 | Method and system for fault testing integrated circuits using a light source | — | 1995-05-30 |
| 5411908 | Flash EEPROM array with P-tank insulated from substrate by deep N-tank | Giovanni Santin, Giovanni Naso, Sebastiano D'Arrigo | 1995-05-02 |
| 5407844 | Process for simultaneously fabricating an insulated gate field-effect transistor and a bipolar transistor | Jack Reynolds | 1995-04-18 |
| 5382536 | Method of fabricating lateral DMOS structure | Satwinder Malhi, Stephen A. Keller | 1995-01-17 |
| 5364801 | Method of forming a charge pump circuit | Luciano Talamonti | 1994-11-15 |
| 5355007 | Devices for non-volatile memory, systems and methods | — | 1994-10-11 |
| 5348895 | LDMOS transistor with self-aligned source/backgate and photo-aligned gate | Manuel J. Torreno, Jr. deceased, George Falessi | 1994-09-20 |
| 5349225 | Field effect transistor with a lightly doped drain | Donald J. Redwine, Mousumi Bhat | 1994-09-20 |
| 5319564 | Method and apparatus for integrated circuit design | Georges Falessi | 1994-06-07 |