Issued Patents All Time
Showing 126–150 of 227 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7923757 | Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate electrode connection through single interconnect level | Scott T. Becker | 2011-04-12 |
| 7917879 | Semiconductor device with dynamic array section | Scott T. Becker | 2011-03-29 |
| 7910959 | Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode connection through single interconnect level | Scott T. Becker | 2011-03-22 |
| 7910958 | Semiconductor device and associated layouts having transistors formed from linear conductive segment with non-active neighboring linear conductive segment | Scott T. Becker | 2011-03-22 |
| 7908578 | Methods for designing semiconductor device with dynamic array section | Scott T. Becker | 2011-03-15 |
| 7906801 | Semiconductor device and associated layouts having transistors formed from six linear conductive segments with intervening diffusion contact restrictions | Scott T. Becker | 2011-03-15 |
| 7901953 | Methods and apparatus for detecting defects in interconnect structures | Shiany Oemardani, Karl F. Smayling | 2011-03-08 |
| 7888705 | Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same | Scott T. Becker | 2011-02-15 |
| 7842975 | Dynamic array architecture | Scott T. Becker | 2010-11-30 |
| 7763534 | Methods, structures and designs for self-aligning local interconnects used in integrated circuits | Scott T. Becker | 2010-07-27 |
| 7590968 | Methods for risk-informed chip layout generation | Scott T. Becker | 2009-09-15 |
| 7459319 | Method and apparatus for characterizing features formed on a substrate | Susie Xiuru Yang, Michael Duane | 2008-12-02 |
| 7446352 | Dynamic array architecture | Scott T. Becker | 2008-11-04 |
| 7332360 | Early detection of metal wiring reliability using a noise spectrum | Dennis Yost | 2008-02-19 |
| RE39697 | Method of making floating-gate memory-cell array with digital logic transistors | Giulio Marotta, Giovanni Santin, Misako A. Matsuoka, Satoru Fukawa | 2007-06-19 |
| 7196350 | Method and apparatus for characterizing features formed on a substrate | Susie Xiuru Yang, Michael Duane | 2007-03-27 |
| 6741333 | Multiple image photolithography system and method | Frank K. Tittel, William L. Wilson | 2004-05-25 |
| 6567153 | Multiple image photolithography system and method | Frank K. Tittel, William L. Wilson | 2003-05-20 |
| 6475846 | Method of making floating-gate memory-cell array with digital logic transistors | Giulio Marotta, Giovanni Santin, Misako A. Matsuoka, Satoru Fukawa | 2002-11-05 |
| 6262914 | Flash memory segmentation | Giulio Marotta, Giovanni Santin | 2001-07-17 |
| 6246102 | Integrated circuits, transistors, data processing systems, printed wiring boards, digital computers, smart power devices, and processes of manufacture | Roland Sauerbrey | 2001-06-12 |
| 6191976 | Flash memory margin mode enhancements | Giulio Marotta, Giovanni Santin | 2001-02-20 |
| 6118706 | Flash memory block or sector clear operation | Giulio Marotta, Giovanni Santin | 2000-09-12 |
| 6060372 | Method for making a semiconductor device with improved sidewall junction capacitance | Alister Young, John Anthony Rodriguez, Jihong Chen | 2000-05-09 |
| 5942374 | Integrated circuits formed in radiation sensitive material and method of forming same | — | 1999-08-24 |