Issued Patents All Time
Showing 151–175 of 227 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5917222 | Intergrated circuit combining high frequency bipolar and high power CMOS transistors | Ronald N. Parker, Manuel L. Torreno, Jr. | 1999-06-29 |
| 5911104 | Integrated circuit combining high frequency bipolar and high power CMOS transistors | Ronald N. Parker, Manuel L. Torreno, Jr. | 1999-06-08 |
| 5907171 | Method of making floating-gate memory-cell array with digital logic transistors | Giovani Santin, Giulio Marotta, Misako A. Matsuoka, Satoru Fukawa | 1999-05-25 |
| 5874849 | Low voltage, high current pump for flash memory | Giulio Marotta, Giovanni Santin, Pietro Piersimoni | 1999-02-23 |
| 5844839 | Programmable and convertible non-volatile memory array | Giulio Marotta, Giovanni Santin, Pietro Piersimoni, Cristina Lattaro | 1998-12-01 |
| 5815026 | High efficiency, high voltage, low current charge pump | Giovanni Santin, Giulio Marotta | 1998-09-29 |
| 5811850 | LDMOS transistors, systems and methods | Manuel L. Torreno, Jr. | 1998-09-22 |
| 5801091 | Method for current ballasting and busing over active device area using a multi-level conductor process | Taylor R. Efland, Satwinder Malhi, Joseph A. Devore, Ross E. Teggatz, Alec J. Morton | 1998-09-01 |
| 5798281 | Method for stressing oxide in MOS devices during fabrication using first and second opposite potentials | — | 1998-08-25 |
| 5798649 | Method for detecting defects in semiconductor insulators | Klaus Alexander Anselm | 1998-08-25 |
| 5767551 | Intergrated circuit combining high frequency bipolar and high power CMOS transistors | Ronald N. Parker, Manuel L. Torreno, Jr. | 1998-06-16 |
| 5732021 | Programmable and convertible non-volatile memory array | Giulio Marotta, Giovanni Santin, Pietro Piersimoni, Cristina Lattaro | 1998-03-24 |
| 5717634 | Programmable and convertible non-volatile memory array | Giulio Marotta, Giovanni Santin, Pietro Piersimoni | 1998-02-10 |
| 5715195 | "Programmable memory verify ""0"" and verify ""1"" circuit and method" | Giulio Marotta, Giovanni Santin, Pietro Piersimoni, Cristina Lattaro | 1998-02-03 |
| 5703807 | EEPROM with enhanced reliability by selectable V.sub.PP for write and erase | Giovanni Santin, Giulio Marotta | 1997-12-30 |
| 5691089 | Integrated circuits formed in radiation sensitive material and method of forming same | — | 1997-11-25 |
| 5689428 | Integrated circuits, transistors, data processing systems, printed wiring boards, digital computers, smart power devices, and processes of manufacture | Roland Sauerbrey | 1997-11-18 |
| 5681768 | Transistor having reduced hot carrier implantation | David A. Baglee | 1997-10-28 |
| 5679968 | Transistor having reduced hot carrier implantation | David A. Baglee | 1997-10-21 |
| 5677041 | Integrated circuits formed in radiation sensitive material and method of forming same | — | 1997-10-14 |
| 5665991 | Device having current ballasting and busing over active area using a multi-level conductor process | Taylor R. Efland, Satwinder Malhi, Joseph A. Devore, Ross E. Teggatz, Alec J. Morton | 1997-09-09 |
| 5656517 | Windowed source and segmented backgate contact linear geometry source cell for power DMOS processes | Taylor R. Efland, Roy Clifton Jones, III, Oh-Kyong Kwon, Satwinder Malhi, Wai Tung Ng | 1997-08-12 |
| 5648275 | Method for detecting defects in semiconductor insulators | Klaus Alexander Anselm | 1997-07-15 |
| 5642295 | Systems utilizing a single chip microcontroller having non-volatile memory devices and power devices | — | 1997-06-24 |
| 5598102 | Method for detecting defects in semiconductor insulators | Klaus Alexander Anselm | 1997-01-28 |