Issued Patents All Time
Showing 26–50 of 306 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12142685 | FinFET device with high-K metal gate stack | Kuo-Cheng Chiang, Ka-Hing Fung, Chih-Sheng Chang | 2024-11-12 |
| 12118707 | System and method for semiconductor topography simulations | Nuo Xu, Zhengping Jiang, Ji-Ting Li, Yuan-Hao Chang, Wen-Hsing Hsieh | 2024-10-15 |
| 12107054 | Semiconductor package, semiconductor device and shielding housing of semiconductor package | Nuo Xu, Yuan-Hao Chang, Po-Sheng Lu | 2024-10-01 |
| D1043443 | Trailer landing leg | Minrui Yang, Shifeng Li | 2024-09-24 |
| 12096544 | Lithography thermal control | Tai-Yu Chen, Cho-Ying Lin, Sagar Deepak Khivsara, Hsiang-Lin Chen, Chieh Hsieh +5 more | 2024-09-17 |
| D1043009 | Base station for cleaning robot | Jinpu Li, Fan Zhang | 2024-09-17 |
| 12087714 | Reduction of cracks in passivation layer | Kuo-An Liu, Wen-Chiung Tu, Yuan-Yang Hsiao, Kai Tak Lam, Chen-Chiu Huang +1 more | 2024-09-10 |
| 12068374 | Method of dopant deactivation underneath gate | Dhanyakumar Mahaveer Sathaiya, Kai-Chieh Yang, Ken-Ichi Goto, Wei-Hao Wu, Yuan-Chen Sun | 2024-08-20 |
| 12040222 | Air-replaced spacer for self-aligned contact scheme | Meng-Yu Lin, Chun-Fu Cheng, Chung-Wei Wu | 2024-07-16 |
| 12029042 | 3D memory device with modulated doped channel | Peng-Chun Liou, Chung-Wei Wu, Yi-Ching Liu, Chia-En Huang | 2024-07-02 |
| D1030460 | Caster | — | 2024-06-11 |
| 12009408 | Multi-gate devices having a semiconductor layer between an inner spacer and an epitaxial feature | Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu | 2024-06-11 |
| 11990522 | Effective work function tuning via silicide induced interface dipole modulation for metal gates | Yen-Tien Tung, Szu-Wei Huang, Zhi-Ren Xiao, Yin-Chuan Chuang, Yung-Chien Huang +3 more | 2024-05-21 |
| 11955554 | Method of fabricating a multi-gate device | Huan-Sheng Wei, Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Chung-Cheng Wu +1 more | 2024-04-09 |
| 11949001 | Multi-gate devices and fabricating the same with etch rate modulation | Chih-Ching Wang, Chung-I Yang, Jon-Hsu Ho, Wen-Hsing Hsieh, Kuan-Lun Cheng +1 more | 2024-04-02 |
| 11942134 | Memory circuit and write method | Huan-Sheng Wei, Tzer-Min Shen | 2024-03-26 |
| 11929409 | Semiconductor device with improved source and drain contact area and methods of fabrication thereof | Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu | 2024-03-12 |
| 11908919 | Multi-gate devices with multi-layer inner spacers and fabrication methods thereof | Chih-Ching Wang, Jon-Hsu Ho, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu | 2024-02-20 |
| 11889674 | Structure and method for SRAM FinFET device having an oxide feature | Kuo-Cheng Ching, Ka-Hing Fung, Chih-Sheng Chang | 2024-01-30 |
| 11862218 | Read circuit for magnetic tunnel junction (MTJ) memory | Gaurav Gupta | 2024-01-02 |
| 11855143 | Semiconductor structures and methods thereof | Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu | 2023-12-26 |
| 11849589 | Semiconductor structure and manufacturing method thereof | Han-Jong Chia, Yu-Ming Lin, Sai-Hooi Yeong | 2023-12-19 |
| 11843032 | Semiconductor device structure with channel and method for forming the same | Huang-Siang LAN, Sathaiya Mahaveer DHANYAKUMAR, Tzer-Min Shen | 2023-12-12 |
| 11769804 | Method of manufacturing semiconductor device and associated memory device | Nuo Xu | 2023-09-26 |
| 11768437 | System and method for performing extreme ultraviolet photolithography processes | Tai-Yu Chen, Sagar Deepak Khivsara, Kuo-An Liu, Chieh Hsieh, Shang-Chieh Chien +5 more | 2023-09-26 |