Issued Patents All Time
Showing 76–95 of 95 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6251694 | Method of testing and packaging a semiconductor chip | Hermen Liu | 2001-06-26 |
| 6214745 | Method of improving surface planarity of chemical-mechanical polishing operation by forming shallow dummy pattern | Ming-Sheng Yang, Juan-Yuan Wu, Water Lur | 2001-04-10 |
| 6211068 | Dual damascene process for manufacturing interconnects | — | 2001-04-03 |
| 6191028 | Method of patterning dielectric | Tri-Rung Yew | 2001-02-20 |
| 6159661 | Dual damascene process | Tri-Rung Yew | 2000-12-12 |
| 6156648 | Method for fabricating dual damascene | — | 2000-12-05 |
| 6156640 | Damascene process with anti-reflection coating | Meng-Jin Tsai | 2000-12-05 |
| 6150073 | Degradation-free low-permittivity dielectrics patterning process for damascene | — | 2000-11-21 |
| 6084304 | Structure of metallization | Tri-Rung Yew | 2000-07-04 |
| 6077769 | Method of fabricating a daul damascene structure | Tony Lin, Tri-Rung Yew | 2000-06-20 |
| 6069066 | Method of forming bonding pad | Tri-Rung Yew | 2000-05-30 |
| 6060379 | Method of forming dual damascene structure | Tri-Rung Yew | 2000-05-09 |
| 6048796 | Method of manufacturing multilevel metal interconnect | Kun-Chih Wang, Wen-Yi Hsieh, Chih-Chien Liu, Water Lur | 2000-04-11 |
| 6027994 | Method to fabricate a dual metal-damascene structure in a substrate | Tri-Rung Yew | 2000-02-22 |
| 6025264 | Fabricating method of a barrier layer | Tri-Rung Yew, Water Lur, Shih-Wei Sun | 2000-02-15 |
| 6001414 | Dual damascene processing method | Hsiao-Pang Chou, Tri-Rung Yew | 1999-12-14 |
| 6001733 | Method of forming a dual damascene with dummy metal lines | Ming-Sheng Yang, Tri-Rung Yew | 1999-12-14 |
| 5990015 | Dual damascence process | Tony Lin, Tri-Rung Yew | 1999-11-23 |
| 5981395 | Method of fabricating an unlanded metal via of multi-level interconnection | Tri-Rung Yew | 1999-11-09 |
| 5959361 | Dielectric pattern | Tri-Rung Yew | 1999-09-28 |