Issued Patents All Time
Showing 301–325 of 364 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7335929 | Transistor with a strained region and method of manufacture | Chun-Chieh Lin, Wen-Chin Lee, Chenming Hu | 2008-02-26 |
| 7319258 | Semiconductor-on-insulator chip with<100>-oriented transistors | Fu-Liang Yang, Hung-Wei Chen, Tim Tsao, Chenming Hu | 2008-01-15 |
| 7312136 | Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance | Chien-Chao Huang, Kuo-Nan Yang, Chun-Chieh Lin, Chenming Hu | 2007-12-25 |
| 7301206 | Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors | Fu-Liang Yang, Chenming Hu | 2007-11-27 |
| 7276763 | Structure and method for forming the gate electrode in a multiple-gate transistor | Fu-Liang Yang | 2007-10-02 |
| 7271431 | Integrated circuit structure and method of fabrication | Chuan-Yi Lin, Shien-Yang Wu | 2007-09-18 |
| 7268024 | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors | How-Yu Chen, Chien-Chao Huang, Wen-Chin Lee, Fu-Liang Yang, Chenming Hu | 2007-09-11 |
| 7262086 | Contacts to semiconductor fin devices | Fu-Liang Yang, Chenming Hu | 2007-08-28 |
| 7238989 | Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement | Chun-Chieh Lin, Fu-Liang Yang, Mong-Song Liang, Chenming Hu | 2007-07-03 |
| 7238581 | Method of manufacturing a semiconductor device with a strained channel | King-Jien Chui, Ganesh Samudra, Jinping Liu, Kheng Chok Tee, Wee Hong Phua +1 more | 2007-07-03 |
| 7226832 | Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer | Chun-Chieh Lin, Fu-Liang Yang, Chen Ming Hu | 2007-06-05 |
| 7214991 | CMOS inverters configured using multiple-gate transistors | Fu-Liang Yang, Chenming Hu | 2007-05-08 |
| 7202139 | MOSFET device with a strained channel | Fu-Liang Yang, Chen Ming Hu | 2007-04-10 |
| 7202122 | Cobalt silicidation process for substrates with a silicon—germanium layer | Chien-Chao Huang, Chao-Hsiung Wang, Chun-Chieh Lin, Chenming Hu | 2007-04-10 |
| 7183593 | Heterostructure resistor and method of forming the same | Wen-Chin Lee, Chih-Hsin Ko, Chung-Hu Ge, Chun-Chieh Lin, Chenming Hu | 2007-02-27 |
| 7180134 | Methods and structures for planar and multiple-gate transistors formed on SOI | Fu-Liang Yang, Chenming Hu | 2007-02-20 |
| 7176092 | Gate electrode for a semiconductor fin device | Hao Chen, Fu-Liang Yang, Chenming Hu | 2007-02-13 |
| 7172943 | Multiple-gate transistors formed on bulk substrates | Fu-Liang Yang, Chenming Hu | 2007-02-06 |
| 7173305 | Self-aligned contact for silicon-on-insulator devices | Fu-Liang Yang, Horng-Huei Tseng, Chenming Hu | 2007-02-06 |
| 7157774 | Strained silicon-on-insulator transistors with mesa isolation | Chenming Hu | 2007-01-02 |
| 7141459 | Silicon-on-insulator ULSI devices with multiple silicon film thicknesses | Fu-Liang Yang, Hao Chen, Carlos H. Diaz, Chenming Hu | 2006-11-28 |
| 7112483 | Method for forming a device having multiple silicide types | Chun-Chieh Lin, Wen-Chin Lee, Chuan-Yi Lin, Chenming Hu | 2006-09-26 |
| 7112495 | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit | Chih-Hsin Ko, Wen-Chin Lee, Chun-Chieh Lin, Chenming Hu | 2006-09-26 |
| 7105894 | Contacts to semiconductor fin devices | Fu-Liang Yang, Chenming Hu | 2006-09-12 |
| 7105908 | SRAM cell having stepped boundary regions and methods of fabrication | Wen-Chin Lee | 2006-09-12 |